Digital Systems Design Using VHDL

3rd Edition Roth

Full download at link: https://testbankpack.com/p/solution-
manual-for-digital-systems-design-using-vhdl-3rd-edition-by-
roth-john-isbn-1305635140-9781305635142/

Chapter 8 Solutions
8.1 function vec2int (vec5: bit_vector(4 downto 0))
return integer is
variable temp: integer := 0;
begin
for i in 4 downto 0 loop
if vec5(i) = '1' then temp := temp + 1; end if;
if i /= 0 then temp := temp*2; end if;
end loop;
return temp;
end vec2int;

It will take 0 simulation time for the function to execute.

8.2 function comp2 (bit_vec: bit_vector; N: integer)

return bit_vector is
variable comp: bit_vector(N-1 downto 0);
variable firstone: boolean;
begin
for i in 0 to N-1 loop
if not firstone then
if bit_vec(i) = '1' then
firstone := true; end if;
comp(i) := bit_vec(i);
else
comp(i) := not bit_vec(i); end if;
end loop;
return comp;
end comp2;

8.3 Assuming the array has a range 0 to N – 1, and integer arrays are defined with:
type IArr is array (natural range <>) of integer;

function LARGEST(ARR: IArr; N: integer)

return integer is
variable max: integer := ARR(0);
begin
for i in 1 to N - 1 loop
if ARR(i) > max then max := ARR(i); end if;
end loop;
return max;
end LARGEST;

8.4 function GT(A, B: bit_vector; N: integer) return boolean is

187
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 begin
for i in N-1 downto 0 loop
if (A(i) and not B(i)) = '1' then return true;
elsif (not A(i) and B(i)) = '1' then return false; end if;
end loop;
return false;
end GT;

8.5 • VHDL functions can only return one value; VHDL procedures can return multiple values
• VHDL function calls replace an expression; VHDL procedure calls are statements
• VHDL procedures can modify the values of their parameters; VHDL functions cannot
• VHDL procedures can have parameters of class variable; VHDL functions cannot

188
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8.6 function BSHIFT(DATA: bit_vector(7 downto 0); N: integer) return bit_vector
is
variable DATAOUT: bit_vector(7 downto 0);
begin
DATAOUT(7 downto N) := DATA(7-N downto 0);
for i in N-1 downto 0 loop
DATAOUT(i) := '0';
end loop;
return DATAOUT;
end BSHIFT;

8.7 function BSHIFT(DATA: bit_vector(7 downto 0); N: integer) return bit_vector

is
variable DATAOUT: bit_vector(7 downto 0);
begin
DATAOUT(7 downto N) := DATA(7-N downto 0);
DATAOUT(N-1 downto 0) := DATA(7 downto 7-N+1);
return DATAOUT;
end BSHIFT;

8.8 function BSHIFT(DATA: bit_vector(7 downto 0); N: integer) return bit_vector

is
variable DATAOUT: bit_vector(7 downto 0);
begin
assert (DATA'length = 8)
report "DATA must be 8 bits wide";
assert ((N >= 0) and (N <= 7))
report "N must be in range 0 to 7";
DATAOUT(7 downto N) := DATA(7-N downto 0);
for i in N-1 downto 0 loop
DATAOUT(i) := '0';
end loop;
return DATAOUT;
end BSHIFT;

8.9 procedure NUMONES(signal bv: in bit_vector;

signal N: in integer range 0 to 31;
signal num: out unsigned(4 downto 0)) is
variable sum: unsigned(4 downto 0) := "00000";
begin
for i in 0 to N-1 loop
if bv(i) = '1' then sum := sum + 1; end if;
end loop;
num <= sum;
end NUMONES;

8.10 procedure SUBVEC(X, Y: in bit_vector;

signal D: inout bit_vector;
signal B,V: out bit;
N: in positive) is
variable bi: bit;
variable Dint: bit_vector(D'range);
begin
for i in 0 to N-1 loop
Dint(i) := X(i) xor Y(i) xor bi;
bi := (not X(i) and bi) or (not X(i) and Y(i)) or (bi and Y(i));
end loop;
B <= bi;
D <= Dint;
V <= (X(N-1) and not Y(N-1) and not Dint(N-1)) or
(not X(N-1) and Y(N-1) and Dint(N-1));
end SUBVEC;

189
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8.11 library IEEE;
use IEEE.numeric_bit.all;

entity addBCD4test is
port(CLK: in bit);
end addBCD4test;

architecture test of addBCD4test is

type BCD4 is array (3 downto 0) of unsigned(3 downto 0);

procedure addBCD4 (add1, add2: in BCD4; cin: in bit;

signal sum: out BCD4; signal cout: out bit) is
variable digit, par1, par2: unsigned(4 downto 0);
variable carry: bit := cin;
begin
for i in 0 to 3 loop
par1 := '0' & add1(i);
par2 := '0' & add2(i);
if carry = '1' then
digit := par1 + par2 + 1;
else
digit := par1 + par2;
end if;
if to_integer(digit) > 9 then
digit := digit + 6;
carry := '1';
else
carry := '0';
end if;
sum(i) <= digit(3 downto 0);
end loop;
cout <= carry;
end addBCD4;

constant par1: BCD4 := ("1000", "1001", "1001", "1001");

constant par2: BCD4 := ("1001", "1001", "1001", "1001");
constant par3: BCD4 := ("0000", "0000", "0000", "0001");
constant par4: BCD4 := ("0011", "0110", "1000", "0001");
constant par5: BCD4 := ("0010", "0111", "1000", "0110");
signal sum1, sum2, sum3, sum4: BCD4;
signal cout1, cout2, cout3, cout4: bit;
begin
process(CLK)
begin
if CLK'event and CLK = '1' then
addBCD4(par1, par3, '0', sum1, cout1);
addBCD4(par2, par3, '0', sum2, cout2);
addBCD4(par4, par5, '0', sum3, cout3);
addBCD4(par4, par5, '1', sum4, cout4);
end if;
end process;
end test;

190
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8.12
Time B C
0 0000 0000
5 0110 0000 call P1
5+∆ 1100 0110
5 + 2∆ 1100 1100
6 1100 1100 call P1
6+∆ 1001 1100 call P1 (process restarted)
6 + 2∆ 0011 1001
6 + 3∆ 0011 0011
7 0011 0011 call P1
7+∆ 0110 0011 call P1 (process restarted)
7 + 2∆ 1100 0110
7 + 3∆ 1100 1100

8.13 X1: True; X2: False; X3: 0 ns; X4: 5 ns

8.14 (a) X1: False; X2: True; X3: 10 ns; X4: 0

(b)

8.15 type intvec is array (natural range <>) of integer;

function DOT (A, B: intvec) return integer is
alias A1: intvec(A'length-1 downto 0) is A;
alias B1: intvec(B'length-1 downto 0) is B;
variable Sum: integer := 0;
begin
assert (A'left = B'left) and (A'right = B'right)
report "Vector ranges are not the same!"
severity warning;
if (A'length /= B'length) then
report "Vector lengths must be equal!"
severity error;
return 0;
end if;
for i in A1'range loop
Sum := Sum + (A1(i) * B1(i));
end loop;
return Sum;
end DOT;

191
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8.16 type matrix is array (natural range <>, natural range <>) of integer;
procedure addM (signal A, B: in matrix; signal C: inout matrix) is
variable A1: matrix(A'length(1)-1 downto 0, A'length(2)-1 downto 0) :=
A;
variable B1: matrix(B'length(1)-1 downto 0, B'length(2)-1 downto 0) :=
B;
variable C1: matrix(C'length(1)-1 downto 0, C'length(2)-1 downto 0) :=
C;
begin
assert A1'length(1) = B1'length(1) and A1'length(2) = B1'length(2)
report "Matrices are not the same size"
severity error;
for i in A1'range(1) loop
for j in A1'range(2) loop
C1(i,j) := A1(i,j) + B1(i,j);
end loop;
end loop;
C <= C1;
end addM;

8.17 procedure Add2 (A, B: in bit_vector;

signal Sum: inout bit_vector; signal V: out bit) is
alias pA: bit_vector(A'length-1 downto 0) is A;
alias pB: bit_vector(B'length-1 downto 0) is B;
variable S: bit_vector(Sum'length-1 downto 0);
variable C: bit;
begin
if S'length < pA'length or S'length < pB'length then V <= '1';
else
for i in S'reverse_range loop
if i < pA'length and i < pB'length then
S(i) := pA(i) xor pB(i) xor C;
C := (pA(i) and pB(i)) or (pA(i) and C) or (pB(i) and C);
elsif i < pA'length and i >= pB'length then
S(i) := pA(i) xor pB(pB'left) xor C;
C := (pA(i) and pB(pB'left)) or (pA(i) and C) or
(pB(pB'left) and C);
elsif i >= pA'length and i < pB'length then
S(i) := pA(pA'left) xor pB(i) xor C;
C := (pA(pA'left) and pB(i)) or (pA(pA'left) and C) or
(pB(i) and C);
else
S(i) := pA(pA'left) xor pB(pB'left) xor C;
C := (pA(pA'left) and pB(pB'left)) or (pA(pA'left) and C) or
(pB(pB'left) and C);
end if;
end loop;
Sum <= S;
if (pA(pA'left) = '0' and pB(pB'left) = '0' and S(S'left) = '1') or
(pA(pA'left) = '1' and pB(pB'left) = '1' and S(S'left) = '0') then
V <= '1'; end if;
end if;
end Add2;

8.18 (a) and (b)

entity P8_14 is
port(A, B: in bit := '1';
C, D: inout bit);
end P8_14;

architecture P8_14 of P8_14 is

192
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 begin
-- 8-14a Solution
process
begin
wait until A'event;
C <= transport not A after 5 ns;
wait for 3 ns;
if B'stable(3 ns) then D <= not D; end if;
end process;

-- 8-14b Solution
process(A, B)
begin
if A'event and A = '1' then -- A has changed
assert B'stable(2 ns) -- False if B has changed w/in past 2ns
report "B not stable for the 2ns before A'event."
severity error;
end if;
if B'event then -- B has changed
assert A'stable(1 ns) -- False if A has changed w/in past 1ns
report "B not stable for the 1ns following A'event."
severity error;
if B = '1' then -- B changed to high
assert (B'delayed'last_event >= 10 ns)
report "B was low for less than 10ns."
severity error;
end if;
end if;
end process;
end P8_14;

8.19 function "<" (A, B: bit_vector) return boolean is

alias In1: bit_vector(A'length-1 downto 0) is A;
alias In2: bit_vector(B'length-1 downto 0) is B;
begin
assert (In1'length = In2'length)
report "Vector lengths must be equal!"
severity error;
for i in In1'range loop
if In1(i) > In2(i) then return FALSE;
elsif In1(i) < In2(i) then return TRUE; end if;
end loop;
return FALSE;
end "<";

8.20 function "-" (A: in bit_vector)

return bit_vector is
variable flag: bit := '0';
variable B: bit_vector(A'length-1 downto 0) := A;
begin
for i in B'reverse_range loop
if flag = '0' and B(i) = '1' then
flag := '1';
elsif flag = '1' then
B(i) := not B(i);
end if;
end loop;
return B;
end "-";

193
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8.21
Time 0 2 4 6 8 10
S(0) Z 0 0 0 Z Z
S(1) Z Z Z Z Z 1
S(2) Z Z 1 0 0 0
R Z 0 X 0 0 X

8.22

8.23 use work.fourpack.all; -- Ref. Figure 8-12, defines X01Z_vector type

entity decoder8 is
port(Addr: in bit_vector;
Check: in X01Z_vector(5 downto 0);
Sel: out bit);
end decoder8;

architecture decoder8 of decoder8 is

alias In1: bit_vector(7 downto 0) is Addr;
alias In2: X01Z_vector(7 downto 2) is Check;
begin
process(In1, In2)
begin
for i in 7 downto 2 loop
if In2(i) = 'X' or (In1(i) = '1' and In2(i) = '1')
or (In1(i) = '0' and In2(i) = '0')
then Sel <= '1';
else Sel <= '0'; exit; end if;
end loop;
end process;
end decoder8;

194
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8.24 library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity OctDFF is
port(D, OE_b, CLK: in std_logic;
Q: out std_logic);
end OctDFF;

architecture OctDFF of OctDFF is

constant tsu: time := 15 ns;
constant th: time := 5 ns;
constant tw: time := 15 ns;
signal store: std_logic;
begin
FF: process(CLK)
begin
if rising_edge(CLK) then
if D = 'Z' then store <= 'X';
else store <= D; end if;
end if;
end process;

Q <= 'Z' when OE_b = '1'

else store when OE_b = '0' and CLK /= 'X'
else 'X';

Check1: process
begin
if falling_edge(CLK) then
assert (CLK'delayed'last_event >= tw)
report "Clock pulse width violation."
severity error;
end if;
wait until rising_edge(CLK);
assert (D'stable(tsu))
report "Setup time violation."
severity error;
wait for th;
assert (D'stable(th))
report "Hold time violation."
severity error;
end process;

Check2: process
begin
wait until falling_edge(CLK);
assert (CLK'delayed'last_event >= tw)
report "Clock pulse width violation."
severity error;
end process;
end OctDFF;

8.25 function MatchVec (A1, B1: std_logic_vector) return boolean is

alias A: std_logic_vector (A1'length-1 downto 0) is A1;
alias B: std_logic_vector (B1'length-1 downto 0) is B1;

begin
if (A'length /= B'length) then
report "Vector lengths are different!"
severity ERROR;
return FALSE;
else

195
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 for i in A'range loop
if ((A(i) = '0' or A(i) = '1' or A(i) = '-') nand
(B(i) = '0' or B(i) = '1' or B(i) = '-')) then
report "Illegal bit value"
severity ERROR;
return FALSE;
else
if not (A(i) = B(i) or A(i) = '-' or B(i) = '-') then
return FALSE; end if;
end if;
end loop;
end if;
return TRUE;
end MatchVec;

8.26 (a)

(b) Note: Problem statement should include “Assume C is initially ‘H’”

(c)
Time S(0) S(1) S(2) C
0 H H H H
4 H H U U
5 H U U U
8 H U 0 U
10 H 1 0 X
14 H 1 Z 1
15 H 0 Z 0
20 H Z Z H
21 Z Z Z Z

8.27
'X' '0' '1' 'L' 'H'
'X' 'X' 'X' 'X' 'X' 'X'
'0' 'X' '0' 'X' '0' '0'
'1' 'X' 'X' '1' '1' '1'
'L' 'X' '0' '1' 'L' 'X'
'H' 'X' '0' '1' 'X' 'H'

8.28 function "not" (vec: std_logic_vector)

return std_logic_vector is
variable inv_vec: std_logic_vector(vec'length-1 downto 0);
alias vector: std_logic_vector(vec'length-1 downto 0) is vec;
begin

196
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 for i in 0 to vec'length-1 loop
inv_vec(i) := not vector(i);
end loop;
return inv_vec;
end function;

8.29

8.30 (a)

(b) library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM_test is
port(CLK: in bit;
Pass, Fail: out bit);
end RAM_test;

architecture RAM_test of RAM_test is

component RAM6116 is
port(Cs_b, We_b, Oe_b: in std_logic;
Address: in unsigned(7 downto 0);

197
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 IO: inout unsigned(7 downto 0));
end component;

signal state, nextstate: integer range 0 to 4 := 0;

signal K, inc, Eq: std_logic := '0';
signal WEb: std_logic := '1';
signal CNTR: unsigned(7 downto 0) := "00000000";
signal RAMbus: unsigned(7 downto 0);
begin
K <= '1' when CNTR = "11111111" else '0';
Eq <= '1' when CNTR = RAMbus else '0'; --comparator
RAMbus <= CNTR when WEb = '0' else "ZZZZZZZZ"; --buffer to RAM IO
RAM: RAM6116 port map ('0', WEb, '0', CNTR, RAMbus);
process(state, K, Eq)
begin
WEb <= '1'; inc <= '0'; Fail <= '0'; Pass <= '0';
case state is
when 0 => WEb <= '0'; nextstate <= 1;
when 1 => inc <= '1';
if K = '0' then nextstate <= 0;
else nextstate <= 2; end if;
when 2 => inc <= '1';
if Eq = '0' then nextstate <= 3;
elsif K = '0' then nextstate <= 2;
else nextstate <= 4; end if;
when 3 => Fail <= '1';
when 4 => Pass <= '1';
end case;
end process;
process(CLK)
begin
if CLK='1' and CLK'event then
state <= nextstate;
if inc = '1' then
if CNTR="11111111" then CNTR <= "00000000";
else CNTR <= CNTR + 1; end if;
end if;
end if;
end process;
end RAM_test;

8.31 See Solution 8.27 (a) and (b)

198
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8.32 (a)

(b)

(c) library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Chex_test is
port(CLK: in bit;
Pass, Fail: out bit);
end Chex_test;

architecture Chex_test of Chex_test is

component RAM6116 is
port(Cs_b, We_b, Oe_b: in std_logic;
Address: in unsigned(7 downto 0);
IO: inout unsigned(7 downto 0));
end component;

199
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 signal state, nextstate: integer range 0 to 4 := 0;
signal K, inc, RP, Eq, setRP: std_logic := '0';
signal WEb: std_logic := '1';
signal CNTR: unsigned(7 downto 0) := "00000000";
signal RAMbus, DATA: unsigned(7 downto 0);
signal evenbit, oddbit: std_logic;
begin
K <= '1' when CNTR = "11111111" else '0';
oddbit <= CNTR(0) xor RP; -- odd bit generator
evenbit <= not oddbit; -- even bit generator
DATA <= oddbit & evenbit & oddbit & evenbit &
oddbit & evenbit & oddbit & evenbit;
Eq <= '1' when Data = RAMbus else '0'; -- comparator
RAMbus <= DATA when WEb = '0' else "ZZZZZZZZ"; -- buffer to RAM IO
RAM: RAM6116 port map ('0', WEb, '0', CNTR, RAMbus);
process(state, K, Eq, RP)
begin
WEb <= '1'; inc <= '0'; Fail <= '0'; Pass <= '0'; setRP <= '0';
case state is
when 0 => WEb <= '0'; nextstate <= 1;
when 1 => inc <= '1';
if K = '0' then nextstate <= 0;
else nextstate <= 2; end if;
when 2 => inc <= '1';
if Eq = '0' then nextstate <= 3;
elsif K = '0' then nextstate <= 2;
elsif RP = '0' then nextstate <= 0; setRP <= '1';
else nextstate <= 4; end if;
when 3 => Fail <= '1';
when 4 => Pass <= '1';
end case;
end process;
process(CLK)
begin
if CLK = '1' and CLK'event then
state <= nextstate;
if setRP = '1' then RP <= '1'; end if;
if inc = '1' then
if CNTR = "11111111" then CNTR <= "00000000";
else CNTR <= CNTR + 1; end if;
end if;
end if;
end process;
end Chex_test;

8.33 entity Tff is

generic(Tplh: time := 8 ns; Tphl: time := 10 ns; Tck: time := 15 ns;
Tsu: time := 4 ns; Th: time := 2 ns);
port(CLK, T: in bit; Q: inout bit := '0'; Qp: inout bit := '1');
end Tff;

architecture behavior of Tff is

signal change: bit;
begin
process(CLK, T)
begin
if CLK'event and CLK = '1' then
if T = '1' then
change <= '1';
assert T'delayed'last_event >= Tsu
report "Setup time violation."
severity warning;

200
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 if Q = '0' then Q <= '1' after Tplh; Qp <= '0' after Tphl;
else Q <= '0' after Tphl; Qp <= '1' after Tplh; end if;
else change <= '0'; end if;
end if;
if CLK'event then
assert CLK'delayed'last_event >= Tck
report "Minimum clock pulse width violation. "
severity warning;
end if;
if change = '1' and T'event then
assert CLK'last_event >= Th
report "Hold time violation."
severity warning;
end if;
end process;
end behavior;

8.34 (a) library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity DFF74LS175 is
generic(constant tplh: time := 30 ns; -- max values by TTL book
constant tphl: time := 30 ns;
constant tsu: time := 20 ns;
constant th: time := 5 ns;
constant tcmin: time := 33 ns); -- 30 MHz clock
port(D, CLR, CLK: in std_logic;
Q, QN: out std_logic);
end DFF74LS175;

architecture DFF74LS175 of DFF74LS175 is

begin
FF: process(CLK, CLR)
begin
if CLR='0' then
Q <= transport '0' after tphl;
QN <= transport '1' after tplh;
elsif CLR='1' then
if rising_edge(CLK) then
if D='1' then
Q <= transport D after tplh;
QN <= transport not D after tphl;
elsif D='0' then
Q <= transport D after tphl;
QN <= transport not D after tplh;
end if;
end if;
else Q <= 'X'; QN <= 'X'; -- when CLR is otherwise
end if;
end process;

Check: process
variable LastRiseTime: time := 0 ns;
begin
wait until rising_edge(CLK);
assert(NOW - LastRiseTime >= tcmin)
report "Clock period violation."
severity error;
LastRiseTime := NOW;
assert(D'stable(tsu))
report "Setup time violation."
severity error;

201
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 wait for th;
assert(D'stable(th))
report "Hold time violation."
severity error;
end process;
end DFF74LS175;

(b) library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity testDFF is
end testDFF;

architecture testDFF of testDFF is

component DFF74LS175
port(D, CLR, CLK: in std_logic;
Q, QN: out std_logic);
end component;

constant tplh: time := 30 ns; -- max values by TTL book

constant tphl: time := 30 ns;
constant tsu: time := 20 ns;
constant th: time := 5 ns;
constant tcmin: time := 33 ns;
constant halfperiod: time := tcmin/2 + 2 ns;

signal CLK: std_logic := '1';

signal D, CLR, Q, QN, CLK2, Q2, QN2: std_logic := '0';

begin
CLK <= not CLK after halfperiod;
DFF1: DFF74LS175 port map (D, CLR, CLK, Q, QN);
DFF2: DFF74LS175 port map (D, CLR, CLK2, Q2, QN2);

process
begin
CLR <= '1';
-- shift 1,0,1 into the flip-flip (test normal shifting)
wait until rising_edge(CLK);
wait for th + 1 ns;
D <= '1'; -- shift 1 in
wait until rising_edge(CLK);
wait for tplh;
assert (Q='1' and QN='0')
report "Wrong value latched."
severity error;
wait until rising_edge(CLK);
wait for th + 1 ns;
D <= '0'; -- shift 0 in
wait until rising_edge(CLK);
wait for tphl;
assert (Q='0' and QN='1')
report "Wrong value latched."
severity error;
wait until rising_edge(CLK);
wait for th + 1 ns;
D <= '1'; -- shift 1 in
wait until rising_edge(CLK);
wait for tplh;
assert (Q='1' and QN='0')
report "Wrong value latched."
severity error;

202
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 -- Test CLR
CLR <= '0';
wait for 5 ns;
CLR <= '1';
if tphl > tplh then
wait for tphl; else wait for tplh; end if;
assert (Q='0' and QN='1')
report "Clear error."
severity error;

-- Test Setup Time Violation

wait until rising_edge(CLK);
wait for th + 1 ns;
D <= '1'; -- shift 1 in
wait for 2 * halfperiod - tsu + 2 ns;
D <= '0';
wait until rising_edge(CLK);

-- Test Hold Time Violation

wait until rising_edge(CLK);
wait for th + 1 ns;
D <= '0'; -- shift 0 in
wait until rising_edge(CLK);
wait for th - 1 ns;
d <= '1';

-- Test Clock Period Violation

wait until rising_edge(CLK); -- wait for D to become stable
CLK2 <= '1';
wait for tcmin/2;
CLK2 <= '0';
wait for tcmin/2 - 1 ns;
CLK2 <= '1';
end process;
end testDFF;

8.35 entity N_comparator is

generic(N: integer := 4);
port(A, B: in bit_vector(N-1 downto 0);
GT, EQ: out bit := '0');
end N_comparator;

architecture N_comparator of N_comparator is

begin
process(A, B)
begin
GT <= '0'; EQ <= '0';
for i in N-1 downto 0 loop
if (A(i) > B(i)) then GT <= '1'; exit;
elsif A(i) = B(i) then EQ <= '1';
else EQ <= '0'; exit; end if;
end loop;
end process;
end N_comparator;

8.36 library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity P8_31 is
port(abus: in bit_vector(14 downto 0);

203
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 dbus: inout std_logic_vector(31 downto 0);
sel, wr: in bit);
end P8_31;

architecture internal of P8_31 is

component SRAM
port(cs_b, we_b, oe_b: in bit;
address: in bit_vector(14 downto 0);
data: inout std_logic_vector(7 downto 0));
end component;
begin
Mem4: for i in 0 to 3 generate
begin
MemX: SRAM port map(address=>abus, data=>dbus(i*8 + 7 downto i * 8),
cs_b=>sel, we_b=>wr, oe_b=>'0');
end generate;
end internal;

8.37 entity DFF is

port(D, Clk, CE: in bit; Q: out bit);
end DFF;

architecture simple of DFF is

begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if CE = '1' then Q <= D; end if;
end if;
end process;
end simple;

entity P8_32 is
generic(N: integer := 4);
port(SI, Sh, CLK: in bit;
Q: inout bit_vector(N downto 1);
SO: out bit);
end P8_32;

architecture internal of P8_32 is

component DFF is
port(D, Clk, CE: in bit; Q: out bit);
end component;
signal D: bit_vector(N downto 0);
begin
D(N) <= SI;
SO <= D(0);
D(N-1 downto 0) <= Q(N downto 1);

FFs: for i in N downto 1 generate

DFFx: DFF port map(D(i), Clk, Sh, Q(i));
end generate;
end internal;

8.38
(a) entity shift_reg is
generic(N: positive := 4; Lshift: Boolean := true);-- generic parameters
used
port(D: in bit_vector(N downto 1);
Qout: out bit_vector(N downto 1);
CLK, Ld, Sh : in bit);
end shift_reg;

204
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 architecture SRN of shift_reg is
signal Q, shifter: bit_vector(N downto 1);
begin
Qout <= Q;
genLS: if Lshift generate -- conditional generate of left shift register
shifter <= Q(N-1 downto 1) & '0';
end generate;
genRS: if not Lshift generate -- conditional generate of right shift
register
shifter <= '0' & Q(N downto 2);
end generate;
process(CLK)
begin
if CLK'event and CLK = '1' then
if LD = '1' then Q <= D;
elsif Sh = '1' then Q <= shifter;
end if;
end if;
end process;
end SRN;

(b) entity shift_reg is

generic(N: positive := 4; Lshift: Boolean := true);-- generic parameters
used
port(D: in bit_vector(N downto 1);
Qout: out bit_vector(N downto 1);
CLK, Ld, Sh : in bit);
end shift_reg;
architecture SRN of shift_reg is
signal Q, shifter: bit_vector(N downto 1);
begin
Qout <= Q;
genLS: if Lshift generate -- conditional generate of left shift register
shifter <= Q(N-1 downto 1) & Q(N);
end generate;
genRS: if not Lshift generate -- conditional generate of right shift
register
shifter <= Q(1) & Q(N downto 2);
end generate;
process(CLK)
begin
if CLK'event and CLK = '1' then
if LD = '1' then Q <= D;
elsif Sh = '1' then Q <= shifter;
end if;
end if;
end process;
end SRN;

8.39 entity P8_33 is

generic(N: integer := 4);
port(A: in bit_vector(N downto 1);
B: in bit;
C: out bit_vector(N downto 1));
end P8_33;

entity and2 is
port(A1, A2: in bit; Z: out bit);
end and2;

architecture internal of P8_33 is

component and2 is

205
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 port(A1, A2: in bit; Z: out bit);
end component;
begin
N_Ands: for i in N downto 1 generate
begin
And2x: and2 port map(A(i), B, C(i));
end generate;
end internal;

architecture internal of and2 is

begin
Z <= A1 and A2;
end internal;

8.40 entity WHITECIRCLE is

port(Ai, Bi: in bit;
Gi, Pi: out bit);
end WHITECIRCLE;

architecture white of WHITECIRCLE is

begin
Gi <= Ai AND Bi;
Pi <= Ai XOR Bi;
end white;

entity BLACKCIRCLE is
port(Gxy, Pxy: out bit;
Gx, Gy, Px, Py: in bit);
end BLACKCIRCLE;

architecture black of BLACKCIRCLE is

begin
Gxy <= Gx OR (Gy AND Px);
Pxy <= Px AND Py;
end black;

entity SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit;
Ci: out bit);
end SEMICIRCLE;

architecture semi of SEMICIRCLE is

begin
Ci <= Gimin1 OR (Pimin1 AND C0);
end semi;

entity SQUARE is
port(Pi, Ci: in bit;
Si: out bit);
end SQUARE;

architecture square of SQUARE is

begin
Si <= Pi XOR Ci;
end square;

entity KOGGESTONE is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end KOGGESTONE;

206
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 architecture koggestone of KOGGESTONE is

component WHITECIRCLE is
port(Ai, Bi: in bit; Gi, Pi: out bit);
end component;
component BLACKCIRCLE is
port(Gxy, Pxy: out bit; Gx, Gy, Px, Py: in bit);
end component;
component SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit; Ci: out bit);
end component;
component SQUARE is
port(Pi, Ci: in bit; Si: out bit);
end component;

signal g0, g1, g2, g3, p0, p1, p2, p3, c: bit_vector(7 downto 0);
signal c_intermediate: bit_vector(7 downto 0);

begin

Gen1: for i in 0 to 7 generate

begin
Stage0: WHITECIRCLE port map(Ai=>A(i), Bi=>B(i), Gi=>g0(i),
Pi=>p0(i));
end generate;

g1(0) <= g0(0);

p1(0) <= p0(0);

Gen2: for i in 1 to 7 generate

begin
Stage1: BLACKCIRCLE port map(Gx=>g0(i), Gy=>g0(i-1), Px=>p0(i),
Py=>p0(i-1), Gxy=>g1(i), Pxy=>p1(i));
end generate;

g2(0) <= g1(0);

g2(1) <= g1(1);
p2(0) <= p1(0);
p2(1) <= p1(1);

Gen3: for i in 2 to 7 generate

begin
Stage2: BLACKCIRCLE port map(Gx=>g1(i), Gy=>g1(i-2), Px=>p1(i),
Py=>p1(i-2),
Gxy=>g2(i), Pxy=>p2(i));
end generate;

g3(0) <= g2(0);

g3(1) <= g2(1);
g3(2) <= g2(2);
g3(3) <= g2(3);
p3(0) <= p2(0);
p3(1) <= p2(1);
p3(2) <= p2(2);
p3(3) <= p2(3);

Gen4: for i in 4 to 7 generate

begin
Stage3: BLACKCIRCLE port map(Gx=>g2(i), Gy=>g2(i-4), Px=>p2(i),
Py=>p2(i-4),
Gxy=>g3(i), Pxy=>p3(i));
end generate;

207
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 Gen5: for i in 0 to 7 generate
begin
Stage4: SEMICIRCLE port map(Gimin1=>g3(i), Pimin1=>p3(i), C0=>Cin,
Ci=>c_intermediate(i));
end generate;

SUM(0) <= Cin XOR p0(0);

Cout <= c_intermediate(7);

Gen6: for i in 1 to 7 generate

begin
Stage5: SQUARE port map(Pi=>p0(i), Ci=>c_intermediate(i-1),
Si=>SUM(i));

end generate;

end koggestone;

8.41 entity WHITECIRCLE is

port(Ai, Bi: in bit;
Gi, Pi: out bit);
end WHITECIRCLE;

architecture white of WHITECIRCLE is

begin
Gi <= Ai AND Bi;
Pi <= Ai XOR Bi;
end white;

entity BLACKCIRCLE is
port(Gxy, Pxy: out bit;
Gx, Gy, Px, Py: in bit);
end BLACKCIRCLE;

architecture black of BLACKCIRCLE is

begin
Gxy <= Gx OR (Gy AND Px);
Pxy <= Px AND Py;
end black;

entity SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit;
Ci: out bit);
end SEMICIRCLE;

architecture semi of SEMICIRCLE is

begin
Ci <= Gimin1 OR (Pimin1 AND C0);
end semi;

entity SQUARE is
port(Pi, Ci: in bit;
Si: out bit);
end SQUARE;

architecture square of SQUARE is

begin
Si <= Pi XOR Ci;
end square;

entity BRENTKUNG is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);

208
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 Cout: OUT bit);
end BRENTKUNG;

architecture brent_kung of BRENTKUNG is

component WHITECIRCLE is
port(Ai, Bi: in bit; Gi, Pi: out bit);
end component;
component BLACKCIRCLE is
port(Gxy, Pxy: out bit; Gx, Gy, Px, Py: in bit);
end component;
component SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit; Ci: out bit);
end component;
component SQUARE is
port(Pi, Ci: in bit; Si: out bit);
end component;

signal g0, g1, g2, g3, p0, p1, p2, p3, c: bit_vector(7 downto 0);
signal c_intermediate: bit_vector(7 downto 0);

begin

Gen1: for i in 0 to 7 generate

begin
Stage0: WHITECIRCLE port map(Ai=>A(i), Bi=>B(i), Gi=>g0(i),
Pi=>p0(i));
end generate;

p1(0) <= p0(0);

p1(2) <= p0(2);
p1(4) <= p0(4);
p1(6) <= p0(6);
g1(0) <= g0(0);
g1(2) <= g0(2);
g1(4) <= g0(4);
g1(6) <= g0(6);

Gen2: for i in 0 to 7 generate

loopGen2: if (((i+1) mod 2) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g0(i), Gy=>g0(i-1), Px=>p0(i),
Py=>p0(i-1), Gxy=>g1(i), Pxy=>p1(i));
end generate;
end generate;

p2(0) <= p1(0);

p2(1) <= p1(1);
p2(2) <= p1(2);
p2(4) <= p1(4);
p2(5) <= p1(5);
p2(6) <= p1(6);
g2(0) <= g1(0);
g2(1) <= g1(1);
g2(2) <= g1(2);
g2(4) <= g1(4);
g2(5) <= g1(5);
g2(6) <= g1(6);

Gen3: for i in 0 to 7 generate

loopGen3: if (((i+1) mod 4) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g1(i), Gy=>g1(i-2), Px=>p1(i),
Py=>p1(i-2), Gxy=>g2(i), Pxy=>p2(i));
end generate;

209
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 end generate;

p3(0) <= p2(0);

p3(1) <= p2(1);
p3(2) <= p2(2);
p3(3) <= p2(3);
p3(4) <= p2(4);
p3(5) <= p2(5);
p3(6) <= p2(6);
g3(0) <= g2(0);
g3(1) <= g2(1);
g3(2) <= g2(2);
g3(3) <= g2(3);
g3(4) <= g2(4);
g3(5) <= g2(5);
g3(6) <= g2(6);

Gen4: for i in 0 to 7 generate

loopGen4: if (((i+1) mod 8) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g2(i), Gy=>g2(i-2), Px=>p2(i),
Py=>p2(i-2), Gxy=>g3(i), Pxy=>p3(i));
end generate;
end generate;

Gen5: for i in 0 to 7 generate

begin
Stage3: SEMICIRCLE port map(Gimin1=>g3(i), Pimin1=>p3(i), C0=>Cin,
Ci=>c_intermediate(i));
end generate;

SUM(0) <= Cin XOR p0(0);

Cout <= c_intermediate(7);

Gen6: for i in 1 to 7 generate

begin
Stage3: SQUARE port map(Pi=>p0(i), Ci=>c_intermediate(i-1),
Si=>SUM(i));
end generate;

end brent_kung;

8.42 entity WHITECIRCLE is

port(Ai, Bi: in bit;
Gi, Pi: out bit);
end WHITECIRCLE;

architecture white of WHITECIRCLE is

begin
Gi <= Ai AND Bi;
Pi <= Ai XOR Bi;
end white;

entity BLACKCIRCLE is
port(Gxy, Pxy: out bit;
Gx, Gy, Px, Py: in bit);
end BLACKCIRCLE;

architecture black of BLACKCIRCLE is

begin
Gxy <= Gx OR (Gy AND Px);
Pxy <= Px AND Py;
end black;

210
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 entity SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit;
Ci: out bit);
end SEMICIRCLE;

architecture semi of SEMICIRCLE is

begin
Ci <= Gimin1 OR (Pimin1 AND C0);
end semi;

entity SQUARE is
port(Pi, Ci: in bit;
Si: out bit);
end SQUARE;

architecture square of SQUARE is

begin
Si <= Pi XOR Ci;
end square;

entity KOGGESTONE is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end KOGGESTONE;

architecture koggestone of KOGGESTONE is

component WHITECIRCLE is
port(Ai, Bi: in bit; Gi, Pi: out bit);
end component;
component BLACKCIRCLE is
port(Gxy, Pxy: out bit; Gx, Gy, Px, Py: in bit);
end component;
component SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit; Ci: out bit);
end component;
component SQUARE is
port(Pi, Ci: in bit; Si: out bit);
end component;

signal g0, g1, g2, g3, p0, p1, p2, p3, c: bit_vector(7 downto 0);
signal c_intermediate: bit_vector(7 downto 0);

begin

Gen1: for i in 0 to 7 generate

begin
Stage0: WHITECIRCLE port map(Ai=>A(i), Bi=>B(i), Gi=>g0(i),
Pi=>p0(i));
end generate;

g1(0) <= g0(0);

p1(0) <= p0(0);

Gen2: for i in 1 to 7 generate

begin
Stage1: BLACKCIRCLE port map(Gx=>g0(i), Gy=>g0(i-1), Px=>p0(i),
Py=>p0(i-1), Gxy=>g1(i), Pxy=>p1(i));
end generate;

g2(0) <= g1(0);

211
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 g2(1) <= g1(1);
p2(0) <= p1(0);
p2(1) <= p1(1);

Gen3: for i in 2 to 7 generate

begin
Stage2: BLACKCIRCLE port map(Gx=>g1(i), Gy=>g1(i-2), Px=>p1(i),
Py=>p1(i-2),
Gxy=>g2(i), Pxy=>p2(i));
end generate;

g3(0) <= g2(0);

g3(1) <= g2(1);
g3(2) <= g2(2);
g3(3) <= g2(3);
p3(0) <= p2(0);
p3(1) <= p2(1);
p3(2) <= p2(2);
p3(3) <= p2(3);

Gen4: for i in 4 to 7 generate

begin
Stage3: BLACKCIRCLE port map(Gx=>g2(i), Gy=>g2(i-4), Px=>p2(i),
Py=>p2(i-4),
Gxy=>g3(i), Pxy=>p3(i));
end generate;

Gen5: for i in 0 to 7 generate

begin
Stage4: SEMICIRCLE port map(Gimin1=>g3(i), Pimin1=>p3(i), C0=>Cin,
Ci=>c_intermediate(i));
end generate;

SUM(0) <= Cin XOR p0(0);

Cout <= c_intermediate(7);

Gen6: for i in 1 to 7 generate

begin
Stage5: SQUARE port map(Pi=>p0(i), Ci=>c_intermediate(i-1),
Si=>SUM(i));

end generate;

end koggestone;

entity KOGGESTONE64 is
generic(k: integer := 2);
port(Ak, Bk: IN bit_vector(8*k-1 downto 0);
Cin: IN bit;
SUMk: OUT bit_vector(8*k-1 downto 0);
Cout: OUT bit);
end KOGGESTONE64;

architecture koggestone64 of KOGGESTONE64 is

component KOGGESTONE is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end component;
signal cin_intermediate, cout_intermediate: bit_vector(k downto 0);
begin

cin_intermediate(0) <= Cin;

212
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 Gen: for i in 0 to k-1 generate
begin
kStage: KOGGESTONE port map(A=>Ak(8*i+7 downto 8*i),B=>Bk(8*i+7
downto 8*i),Cin=>cin_intermediate(i),SUM=>SUMk(8*i+7 downto
8*i),Cout=>cout_intermediate(i));
cin_intermediate(i+1) <= cout_intermediate(i);
end generate;
Cout <= cout_intermediate(k-1);

end koggestone64;

8.43 entity WHITECIRCLE is

port(Ai, Bi: in bit;
Gi, Pi: out bit);
end WHITECIRCLE;

architecture white of WHITECIRCLE is

begin
Gi <= Ai AND Bi;
Pi <= Ai XOR Bi;
end white;

entity BLACKCIRCLE is
port(Gxy, Pxy: out bit;
Gx, Gy, Px, Py: in bit);
end BLACKCIRCLE;

architecture black of BLACKCIRCLE is

begin
Gxy <= Gx OR (Gy AND Px);
Pxy <= Px AND Py;
end black;

entity SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit;
Ci: out bit);
end SEMICIRCLE;

architecture semi of SEMICIRCLE is

begin
Ci <= Gimin1 OR (Pimin1 AND C0);
end semi;

entity SQUARE is
port(Pi, Ci: in bit;
Si: out bit);
end SQUARE;

architecture square of SQUARE is

begin
Si <= Pi XOR Ci;
end square;

entity BRENTKUNG is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end BRENTKUNG;

architecture brent_kung of BRENTKUNG is

213
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 component WHITECIRCLE is
port(Ai, Bi: in bit; Gi, Pi: out bit);
end component;
component BLACKCIRCLE is
port(Gxy, Pxy: out bit; Gx, Gy, Px, Py: in bit);
end component;
component SEMICIRCLE is
port(Gimin1, Pimin1, C0: in bit; Ci: out bit);
end component;
component SQUARE is
port(Pi, Ci: in bit; Si: out bit);
end component;

signal g0, g1, g2, g3, p0, p1, p2, p3, c: bit_vector(7 downto 0);
signal c_intermediate: bit_vector(7 downto 0);

begin

Gen1: for i in 0 to 7 generate

begin
Stage0: WHITECIRCLE port map(Ai=>A(i), Bi=>B(i), Gi=>g0(i),
Pi=>p0(i));
end generate;

p1(0) <= p0(0);

p1(2) <= p0(2);
p1(4) <= p0(4);
p1(6) <= p0(6);
g1(0) <= g0(0);
g1(2) <= g0(2);
g1(4) <= g0(4);
g1(6) <= g0(6);

Gen2: for i in 0 to 7 generate

loopGen2: if (((i+1) mod 2) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g0(i), Gy=>g0(i-1), Px=>p0(i),
Py=>p0(i-1), Gxy=>g1(i), Pxy=>p1(i));
end generate;
end generate;

p2(0) <= p1(0);

p2(1) <= p1(1);
p2(2) <= p1(2);
p2(4) <= p1(4);
p2(5) <= p1(5);
p2(6) <= p1(6);
g2(0) <= g1(0);
g2(1) <= g1(1);
g2(2) <= g1(2);
g2(4) <= g1(4);
g2(5) <= g1(5);
g2(6) <= g1(6);

Gen3: for i in 0 to 7 generate

loopGen3: if (((i+1) mod 4) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g1(i), Gy=>g1(i-2), Px=>p1(i),
Py=>p1(i-2), Gxy=>g2(i), Pxy=>p2(i));
end generate;
end generate;

p3(0) <= p2(0);

p3(1) <= p2(1);

214
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 p3(2) <= p2(2);
p3(3) <= p2(3);
p3(4) <= p2(4);
p3(5) <= p2(5);
p3(6) <= p2(6);
g3(0) <= g2(0);
g3(1) <= g2(1);
g3(2) <= g2(2);
g3(3) <= g2(3);
g3(4) <= g2(4);
g3(5) <= g2(5);
g3(6) <= g2(6);

Gen4: for i in 0 to 7 generate

loopGen4: if (((i+1) mod 8) = 0) generate
Stage1: BLACKCIRCLE port map(Gx=>g2(i), Gy=>g2(i-2), Px=>p2(i),
Py=>p2(i-2), Gxy=>g3(i), Pxy=>p3(i));
end generate;
end generate;

Gen5: for i in 0 to 7 generate

begin
Stage3: SEMICIRCLE port map(Gimin1=>g3(i), Pimin1=>p3(i), C0=>Cin,
Ci=>c_intermediate(i));
end generate;

SUM(0) <= Cin XOR p0(0);

Cout <= c_intermediate(7);

Gen6: for i in 1 to 7 generate

begin
Stage3: SQUARE port map(Pi=>p0(i), Ci=>c_intermediate(i-1),
Si=>SUM(i));
end generate;

end brent_kung;

entity BRENTKUNG64 is
generic(k: integer := 2);
port(Ak, Bk: IN bit_vector(8*k-1 downto 0);
Cin: IN bit;
SUMk: OUT bit_vector(8*k-1 downto 0);
Cout: OUT bit);
end BRENTKUNG64;

architecture brentkung64 of BRENTKUNG64 is

component BRENTKUNG is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end component;
signal cin_intermediate, cout_intermediate: bit_vector(k downto 0);

begin
cin_intermediate(0) <= Cin;
Gen: for i in 0 to k-1 generate
begin
kStage: BRENTKUNG port map(A=>Ak(8*i+7 downto 8*i),B=>Bk(8*i+7 downto
8*i),Cin=>cin_intermediate(i),SUM=>SUMk(8*i+7
downto 8*i),Cout=>cout_intermediate(i));
cin_intermediate(i+1) <= cout_intermediate(i);
end generate;

215
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 Cout <= cout_intermediate(k-1);
end brentkung64;

8.44 entity eight_bit_adder is

generic(k: integer := 0);
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end eight_bit_adder;

architecture adder of eight_bit_adder is

component KOGGESTONE is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end component;

component BRENTKUNG is
port(A, B: IN bit_vector(7 downto 0);
Cin: IN bit;
SUM: OUT bit_vector(7 downto 0);
Cout: OUT bit);
end component;
begin

if k = 1 generate
GenKoggeStone: KOGGESTONE(A=>A,B=>B,Cin=>Cin,SUM=>SUM,Cout=>Cout);
if k = 0 generate
GenBrentKung: BRENTKUNG(A=>A,B=>B,Cin=>Cin,SUM=>SUM,Cout=>Cout);

end architecture;

8.45 entity and2 is

port(A1, A2: in bit; Z: out bit);
end and2;

architecture internal of and2 is

begin
Z <= A1 and A2;
end internal;

entity HA is
port(A, B: in bit; S, Co: out bit);
end HA;

architecture internal of HA is
begin
Co <= A and B;
S <= A xor B;
end internal;

entity FA is
port(A, B, Ci: in bit; S, Co: out bit);
end FA;

architecture internal of FA is
begin
S <= A xor B xor Ci;
Co <= (A and B) or (A and Ci) or (B and Ci);
end internal;

216
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 entity P8_34 is
port(X, Y: in bit_vector(3 downto 0);
P: out bit_vector(7 downto 0));
end P8_34;

architecture array_mult of P8_34 is

type bv_arr1 is array (0 to 3) of bit_vector(3 downto 0);
type bv_arr2 is array (1 to 3) of bit_vector(3 downto 0);
signal and_gate_out: bv_arr1;
signal adder_sum_out: bv_arr1;
signal adder_carry_out: bv_arr2;
component and2 is
port(A1, A2: in bit; Z: out bit);
end component;
component HA is
port(A, B: in bit; S, Co: out bit);
end component;
component FA is
port(A, B, Ci: in bit; S, Co: out bit);
end component;
begin
--create 16 and gates
androw: for i in 0 to 3 generate
andcol: for j in 3 downto 0 generate
And2x: And2 port map(X(j), Y(i), and_gate_out(i)(j));
end generate;
end generate;

adder_sum_out(0) <= and_gate_out(0); --row 0 has no adders

--create half-adders at end of row

HAs: for i in 1 to 3 generate
HAx: HA port map(adder_sum_out(i-1)(1), and_gate_out(i)(0),
adder_sum_out(i)(0), adder_carry_out(i)(0));
end generate;

--create half-adder at far left of second row

HAfl: HA port map(and_gate_out(1)(3), adder_carry_out(1)(2),
adder_sum_out(1)(3), adder_carry_out(1)(3));

--create full-adders at far left of third and fourth row

FAs: for i in 2 to 3 generate
FAx: FA port map(and_gate_out(i)(3), adder_carry_out(i-1)(3),
adder_carry_out(i)(2),
adder_sum_out(i)(3), adder_carry_out(i)(3));
end generate;

--generate 2 full-adders in middle of each row

FArow: for i in 1 to 3 generate
FAcol: for j in 2 downto 1 generate
FAn: FA port map(and_gate_out(i)(j), adder_sum_out(i-1)(j+1),
adder_carry_out(i)(j-1),
adder_sum_out(i)(j), adder_carry_out(i)(j));
end generate;
end generate;

P(7) <= adder_carry_out(3)(3);

P(6 downto 3) <= adder_sum_out(3)(3 downto 0);
P(2) <= adder_sum_out(2)(0);
P(1) <= adder_sum_out(1)(0);
P(0) <= and_gate_out(0)(0);
end array_mult;

217
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
8.46 use std.textio.all;

entity P8_35 is
end P8_35;

architecture internal of P8_35 is

file in_file: text open read_mode is "FILE2.txt";
type iarr is array (natural range <>) of integer;
begin
process
variable buff: line;
variable B: iarr(0 to 4);
begin
readline(in_file, buff);
for i in 0 to 4 loop
read(buff, B(i));
end loop;
-- do something useful with the data
end process;
end internal;

8.47 use std.textio.all;

procedure timer_delay (signal sig: out integer; constant name: in string)

is
file in_file: text open read_mode is name;
variable buff: line;
variable input_time: time;
variable input_value: integer;
begin
while (not endfile(in_file)) loop
readline(in_file, buff);
read(buff, input_time);
wait for input_time;
read(buff, input_value);
sig <= input_value;
end loop;
end procedure;

8.48 use std.textio.all;

procedure logger (signal sig: in bit_vector; constant name: in string) is

file output_file: text open write_mode is name;
variable buff: line;
begin
loop
write(buff, sig, right, sig'length + 1);
write(buff, NOW, right, 8);
writeline(output_file, buff);
wait until sig'event;
end loop;
end procedure;

218
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
 219
© 2018 Cengage Learning®. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.