21CSS201T – COMPUTER

ORGANIZATION AND
ARCHITECTURE
UNIT – 2
Functional Units of a Computer
Computer:
It is defined as a fast electronic calculating
machine that accepts digitized input
information , processed it according to
internally stored instructions , and produces
the resulting output information.
The list of instructions is called program.
The internal storage is called as memory.
Types of Computer: - usage
1.Personal computer – homes, schools, business
2.Desktop computer – homes and office desk
3.Notebook computer – all components packed into
briefcase - compact size – schools , offices
4.Workstations – engineering applications ,
interactive design work
5.Mainframes – supercomputers - used in
enterprises
 FUNCTIONAL UNITS OF COMPUTER
• Input Unit

• Output Unit

• ALU

• Control Units

• Memory
 The Big Picture

Processor
Input
Control
Memory

ALU
Output

Since 1946 all computers have had 5 components!!!

 IMPORTANT
Function SLIDE !

• ALL computer functions are:

– Data PROCESSING
– Data STORAGE Data = Information
– Data MOVEMENT
– CONTROL Coordinates How
Information is Used
INPUT UNIT:

•Converts the external world data to a binary format, which can

be understood by CPU

•Eg: Keyboard, Mouse, Joystick etc

OUTPUT UNIT:

•Converts the binary format data to a format that a common

man can understand

•Eg: Monitor, Printer, LCD, LED etc

Control unit:
•The “brain” of the machine

•Responsible for carrying out computational task

•CU Provides control signals in accordance with some
timings which in turn controls the execution process

•Contains ALU, CU, Registers

ALU:

•ALU Performs Arithmetic and logical operations

•Register Stores data and result and speeds up the

operation
Example
Add R1, R2

T1 Enable R1

T2 Enable R2

T3 Enable ALU for addition operation

T4
 •Control unit works with a
reference signal called
T1
processor clock

T2 •Processor divides the

operations into basic steps

R1 R2
•Each basic step is
executed in one clock
cycle

R2
MEMORY

•Stores data, results, programs

•Two class of storage

(i) Primary (ii) Secondary

•Two types are RAM or R/W memory and ROM read only memory

•ROM is used to store data and program which is not going to change.

•Secondary storage is used for bulk storage or mass storage

 Basic Operational Concepts

Basic Function of Computer

• To Execute a given task as per the appropriate program

• Program consists of list of instructions stored in

memory
 Review
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of a
list of instructions is stored in the memory.
• Individual instructions are brought from the memory into
the processor, which executes the specified operations.
• Data to be used as operands are also stored in the
memory.
 A Typical Instruction
• Add LOCA, R0
• Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and added to
the contents of R0 – the resulting sum is stored in
register R0.
 Separate Memory Access and ALU
Operation
• Load LOCA, R1
• Add R1, R0
• Whose contents will be overwritten?
Interconnection between Processor and Memory
Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are

❑ Two registers-MAR (Memory Address Register) and

MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
❑ Instruction register (IR) : Hold the Instructions that is
currently being executed
❑ Program counter: Points to the next instructions that is
to be fetched from memory
•(PC) (MAR)( the contents of PC transferred to MAR)

•(MAR) (Address bus) Select a particular memory

location

•Issues RD control signals

•Reads instruction present in memory and loaded into MDR

•Will be placed in IR (Contents transferred from MDR to IR)

•Instruction present in IR will be decoded by which
processor understand what operation it has to perform

•Increments the contents of PC by 1, so that it points to the

next instruction address

•If data required for operation is available in register, it

performs the operation

•If data is present in memory following sequence is

performed
•Address of the data MAR

•MAR select memory location where is issued RD

signal

•Reads data via data bus MDR

•From MDR data can be directly routed to ALU or it can be

placed in register and then operation can be performed

•Results of the operation can be directed towards output

device, memory or register

•Normal execution preempted (interrupt)

 Interrupt
• An interrupt is a request from I/O device for
service by processor
• Processor provides requested service by
executing interrupt service routine (ISR)
• Contents of PC, general registers, and some
control information are stored in memory .
• When ISR completed, processor restored, so
that interrupted program may continue
 BUS STRUCTURE
Connecting CPU and memory
The CPU and memory are normally connected by three
groups of connections, each called a bus: data bus, address
bus and control bus

Connecting CPU and memory using three buses

 BUS STRUCTURE
•Group of wires which carries information form CPU to peripherals or vice
– versa

•Single bus structure: Common bus used to communicate between

peripherals and microprocessor

INPUT MEMORY PROCESSOR OUTPUT

SINGLE BUS STRUCTURE

Continued:-

• To improve performance multibus structure can be used

•In two – bus structure : One bus can be used to fetch

instruction other can be used to fetch data, required for
execution.

•Thus improving the performance ,but cost increases

 A2 A1 A0 Selected
CONTROL BUS location

0 0 0 0th Location
0 0 1 1st Location
0 1 0

W/R
CS RD 0 1 1
A0 PROCESSOR
A1 1 0 0
A2
1 0 1
ADDRESS BUS
1 1 0
D7 D0
D0 D7
1 1 1

DATA BUS
Cont:-

•23 = 8 i.e. 3 address line is required to select 8 location

•In general 2x = n where x number of address lines

(address bit) and n is number of location

•Address bus : unidirectional : group of wires which

carries address information bits form processor to
peripherals (16,20,24 or more parallel signal lines)
Cont:-

•Databus: bidirectional : group of wires which

carries data information bit form processor to
peripherals and vice – versa

•Controlbus: bidirectional: group of wires which

carries control signals form processor to
peripherals and vice – versa

•Figure below shows address, data and control bus

and their connection with peripheral and
microprocessor
Memory Locations,
Addresses, and
Operations
 Memory Location,
Addresses, and
Operation n bits
first word
• Memory consists of
second word
many millions of
storage cells, each
•
of which can store 1 •
bit. •

• Data is usually i th word

accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure: Memory words.

 MEMORY LOCATIONS AND ADDRESSES
•Main memory is the second major subsystem in a
computer. It consists of a collection of storage locations,
each with a unique identifier, called an address.

•Data is transferred to and from memory in groups of

bits called words. A word can be a group of 8 bits, 16
bits, 32 bits or 64 bits (and growing).

•If the word is 8 bits, it is referred to as a byte. The term

“byte” is so common in computer science that
sometimes a 16-bit word is referred to as a 2-byte word,
or a 32-bit word is referred to as a 4-byte word.
Main memory
 Address space

•To access a word in memory requires an identifier. Although

programmers use a name to identify a word (or a collection
of words), at the hardware level each word is identified by an
address.

•The total number of uniquely identifiable locations in

memory is called the address space.

•For example, a memory with 64 kilobytes (16 address line

required) and a word size of 1 byte has an address space that
ranges from 0 to 65,535.
i
Memory addresses are defined using unsigned
binary integers.
 MEMORY OPERATIONS
• Today, general-purpose computers use a set of instructions called a
program to process data.

• A computer executes the program to create output data from input

data

• Both program instructions and data operands are stored in memory

• Two basic operations requires in memory access

• Load operation (Read or Fetch)-Contents of specified
memory location are read by processor
• Store operation (Write)- Data from the processor is stored in
specified memory location
 Assignment of Byte Address
• Big-endian and little-endian are terms that
describe the order in which a sequence of
bytes are stored in computer memory. Big-
endian is an order in which the "bigend"
(most significant value in the sequence) is
stored first (at the lowest storage address).
•
 Assignment of byte addresses
• Little Endian (e.g., in DEC, Intel)
» low order byte stored at lowest address
» byte0 byte1 byte2 byte3

• Eg: 46,78,96,54 (32 bit data)

• H BYTE L BYTE

• 8000 54
• 8001 96
• 8002 78
• 8003
46
• 8004
|
 Big Endian
• Big Endian (e.g., in IBM, Motorolla, Sun, HP)
» high order byte stored at lowest address
» byte3 byte2 byte1 byte0

• Programmers/protocols should be careful

when transferring binary data between Big
Endian and Little Endian machines
Big-Endian and Little-
Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the
word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

• In case of 16 bit data, aligned words begin at
byte addresses of 0,2,4,………………………….
• In case of 32 bit data, aligned words begin at
byte address of 0,4,8,………………………….
• In case of 64 bit data, aligned words begin at
byte addresses of 0,8,16,………………………..
• In some cases words can start at an arbitrary
byte address also then, we say that word
locations are unaligned
 Instruction and
Instruction Sequencing
• INSTRUCTION SET ARCHITECTURE:-Complete
instruction set of the processor

• BASIC 4 TYPES OF OPERATION:-

• Data transfer between memory and
processor register
• Arithmetic and logic operation
• Program sequencing and control
• I/O transfer
 Register transfer notation (RTN)
Transfer between processor registers & memory, between
processor register & I/O devices

Memory locations, registers and I/O register names are

identified by a symbolic name in uppercase alphabets

• LOC,PLACE,MEM are the address of memory location

• R1 , R2,… are processor registers
• DATA_IN, DATA_OUT are I/O registers
•Contents of location is indicated by using square
brackets [ ]

•RHS of RTN always denotes a values, and is called

Source

•LHS of RTN always denotes a symbolic name where

value is to be stored and is called destination

•Source contents are not modified

•Destination contents are overwritten

 Examples of RTN statements

• R2 [LOCN]

• R4 [R3] +[R2]
 ASSEMBLY LANGUAGE NOTATION (ALN)

• RTN is easy to understand and but cannot be

used to represent machine instructions
• Mnemonics can be converted to machine
language, which processor understands
using assembler
Eg:
1. MOVE LOCN, R2
2. ADD R3, R2, R4
 TYPES OF INSTRUCTION
➢Three address instruction

•Syntax: Operation source 1, source 2, destination

•Eg: ADD D,E,F where D,E,F are memory location
•Advantage: Single instruction can perform the
complete operation
•Disadvantage : Instruction code will be too large to fit
in one word location in memory
TWO ADDRESS INSTRUCTION
•Syntax : Operation source, destination

•Eg: MOVE E,F MOVE D,F

ADD D,F OR ADD E,F

Perform ADD A,B,C using 2 instructions

MOVE B,C
ADD A,C

❖Disadvantage: Single instruction is not sufficient to perform

the entire operation.
 ONE ADDRESS INSTRUCTION

• Syntax- Operation source/destination

• In this type either a source or destination
operand is mentioned in the instruction
• Other operand is implied to be a processor
register called Accumulator
• Eg: ADD B (general)
• Load D; ACC [memlocation _D]
• ADD E; ACC (ACC) +(E)
• STORE F; memlocation_ F (ACC )
 Zero address instruction

• Location of all operands are defined implicitly

• Operands are stored in a structure called

pushdown stack
 Continued
➢ If processor supports ALU operations one data in memory and
other in register then the instruction sequence is
• MOVE D, Ri
• ADD E, Ri
• MOVE Ri, F
➢ If processor supports ALU operations only with registers then
one has to follow the instruction sequence given below
• LOAD D, Ri
• LOAD E, Rj
• ADD Ri, Rj
• MOVE Rj, F
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
 Basic Instruction Cycle
• Basic computer operation cycle
– Fetch the instruction from memory into a control
register (PC)
– Decode the instruction
– Locate the operands used by the instruction
– Fetch operands from memory (if necessary)
– Execute the operation in processor registers
– Store the results in the proper place
– Go back to step 1 to fetch the next instruction
 INSTRUCTION EXECUTION & STRIAGHT LINE
SEQUENCING
Address Contents

}
Begin execution here i Move A,R0
i+4 Add B,R0
3-instruction program
i+8 Move R0,C
. segment
.
.

A
.
.
.

B Data for Program

. C [A]+[B]
.

C
• PC – Program counter: hold the address of the next
instruction to be executed
• Straight line sequencing: If fetching and executing of
instructions is carried out one by one from successive
addresses of memory, it is called straight line sequencing.
• Major two phase of instruction execution
• Instruction fetch phase: Instruction is fetched form
memory and is placed in instruction register IR
• Instruction execute phase: Contents of IR is decoded and
processor carries out the operation either by reading
data from memory or registers.
 BRANCHING

A straight line program for adding n numbers

Using a loop to add n numbers

 BRANCHING
• Branch instruction are those which changes the
normal sequence of execution.

• Sequence can be changed either conditionally or

unconditionally.

• Accordingly we have conditional branch instructions

and unconditional branch instruction.

• Conditional branch instruction changes the sequence

only when certain conditions are met.

• Unconditional branch instruction changes the

sequence of execution irrespective of condition of
the results.
 CONDITION CODES
➢ CONDITIONAL CODE FLAGS: The processor keeps track of
information about the results of various operations for
use by subsequent conditional branch instructions

• N – Negative 1 if results are Negative

0 if results are Positive
• Z – Zero 1 if results are Zero
0 if results are Non zero
• V – Overflow 1 if arithmetic overflow occurs
0 non overflow occurs
• C – Carry 1 if carry and from MSB bit
0 if there is no carry from MSB bit
 Conditional Branch
Instructions
A: 11110000
• Example:
A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 1

B: 0 0 0 1 0 1 0 0 11011101

C=1 Z=0

V=0
Overflow occurs when the magnitude of a
number exceeds the range allowed by the size of
the bit field
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Figure Format and different instruction types
 Processing the instructions
Simple computer, like most computers, uses machine cycles.

A cycle is made of three phases: fetch, decode and execute.

During the fetch phase, the instruction whose address is determined by

the PC is obtained from the memory and loaded into the IR. The PC is
then incremented to point to the next instruction.

During the decode phase, the instruction in IR is decoded and the

required operands are fetched from the register or from memory.

During the execute phase, the instruction is executed and the results are
placed in the appropriate memory location or the register.

Once the third phase is completed, the control unit starts the cycle again,
but now the PC is pointing to the next instruction.
The process continues until the CPU reaches a HALT instruction.
 Types of Addressing Modes
The different ways in which the location of the operand is specified in an
instruction are referred to as addressing modes

• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Displacement addressing
1.Relative Addressing
2.Indexed Addressing
3.Base Register addressing
• Stack addressing mode
1.Auto increment
2.Auto decrement
 NOTATIONS USED IN ADDRESSING
MODES
A- contents of an address field in an instruction.
R- contents of an address field in an instruction
that refers to a register.
EA-Actual effective address of the location
containing the referenced operand.
(X)- contents of the memory location X or
register X
 Immediate Addressing
• Operand is given explicitly in the instruction
• Operand = Value
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range of size of the operand.

Instruction
opcode
operand
 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
 Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand
 Indirect Addressing
• Memory cell pointed to by address field
contains the address of (pointer to) the
operand
• EA = [A]
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator
 Indirect Addressing
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand
 Register Addressing
• Similar to direct addressing mode
• Operand is held in register named in address
field
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
 Register Addressing
• No memory access

• Very fast execution

• Very limited address space

• Multiple registers helps performance

– Requires good assembly programming or compiler
writing
 Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand
 Register Indirect Addressing
• Similar to indirect addressing
• EA = [R]
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing
Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 Displacement addressing mode
• It combines the capabilities of direct addressing
modes and register indirect addressing mode.
• EA=A+(R)
• Three types of displacement addressing mode:
• 1.Indexed addressing
• 2.Relative addressing
• 3.Base Register addressing mode
 Indexed Addressing
• A version of displacement addressing.
• EA = X + [R]
• Address field hold two values
– X = constant value (offset)
– R = register that holds address of memory
locations
– or vice versa
(Offset given as constant or in the index register)
Add 20(R1),R2 or Add 1000(R1),R2
Indexed Addressing Diagram
Instruction
Opcode Register R Constant Value
Memory

Registers

Pointer to Operand + Operand

 Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = X + (PC)
• i.e. get operand from X bytes away from
current location pointed to by PC
• locality of reference & cache usage
 Base Register Addressing mode
• The referenced register contains a main
memory address and the address field
contains the displacement(offset value) from
that address.
• The referenced register may be implicit or
explicit.
 Stack addressing mode
Types of stack addressing mode:
1.Auto increment addressing mode
2.Auto decrement addressing mode
 Auto increment mode
• The effective address of the operand is the
contents of a register specified in the instruction.
• After accessing the operand, the contents of this
register are automatically incremented to point
to the next item in the list
• EA=[Ri]; Increment Ri ---- (Ri)+
Eg: Add (R2)+,R0
 Auto decrement mode
• The contents of a register specified in the
instruction are first automatically
decremented and are then used as the
effective address of the operand

• Decrement Ri; EA= [Ri] ----- -(Ri)

What is a Microprocessor???

Program controlled semiconductor device (IC) which fetches (from

memory), decodes and executes instructions.

It is used as CPU (Central Processing Unit) in computers.

1
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
2
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
Functional blocks
Various conditions of the
Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and 3

microprocessor control unit

 8086 Microprocessor: Overview
First 16- bit processor released by INTEL in the year 1978

Approximately 29, 000 transistors, 40 pin DIP, 5V supply

20-bit address to access memory  can address up to 220 = 1 megabytes of memory space.

Addressable memory space is organized in to two banks of 512 kb each; Even (or lower) bank
and Odd (or higher) bank. Address line A0 is used to select even bank and control signal BHE is
used to access odd bank

Uses a separate 16 bit address for I/O mapped devices  can generate 216 = 64 k addresses.

Operates in two modes: minimum mode and maximum mode, decided by the signal at MN and
MX pins. 4
Pins and signals
8086 Microprocessor
Common signals

AD0-AD15 (Bidirectional)
Pins and Signals
Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
6
8086 Microprocessor
Common signals

BHE (Active Low)/S7 (Output)

Pins and Signals
Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an input signal.
It is active when low.
7
8086 Microprocessor
Common signals

TEST
Pins and Signals
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’
instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
8

The signal is active high.

8086 Microprocessor
Common signals

RESET (Input)
Pins and Signals
Causes the processor to immediately
terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

9
synchronized.
8086 Microprocessor: Pins and Signals
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

10
8086 Microprocessor: Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports. 11
BIU and EU functions separately.
8086 Microprocessor: Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag

Parity Flag
This flag is set, when the This flag is set, if the result of
This flag is set to 1, if the lower
result of any computation the computation or comparison
byte of the result contains even
is negative performed by an instruction is
number of 1’s ; for odd number
zero
of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address 12
disables these interrupts.
towards the lowest address, i.e., auto incrementing mode.
8086 Microprocessor: Architecture Registers
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register 13

8086 Microprocessor: Architecture Registers and
Special Functions
Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access
memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data)
14
for string operations
INSTRUCTION SET
8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

Data Transfer Instructions

Arithmetic Instructions

Logical Instructions

String manipulation Instructions

Process Control Instructions

Control Transfer Instructions

16
DATA TRANSFER
INSTRUCTIONS:
Used to transfer data to and
fro from the source operand
and desti ation operans.
Types of Instructions
⚫ Data Transfer Instructions

Name Mnemonic Data value is

not modified
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Type of Mnemonics Syntax
Instruction

MOV MOV reg2/ mem, reg1/ mem e.g. MOV reg2, reg1
MOV reg/ mem, data e.g. MOV reg, data

XCHG XCHG reg2/ mem, reg1 e.g. XCHG loc1, loc2

PUSH PUSH reg16/ mem e.g. PUSH reg16

Data Transfer
Instructions POP POP reg16/ mem e.g. POP reg16

IN IN A, [DX] e.g. IN AL, [DX]

OUT OUT [DX], A e.g. OUT [DX], AL

19
ARITHMATIC INSTRUCTIONS:
Used to perform arithmetic
operations.
Type of Instruction Mnemonics Syntax

ADD ADD reg2/ mem, reg1/mem e.g. ADD reg2, reg1

ADD reg/mem, data e.g. ADD reg, data
ADD A, data e.g. ADD AL, data8
ADC ADC reg2/ mem, reg1/mem e.g. ADC reg2, reg1
ADC reg/mem, data e.g. ADC reg, data
ADDC A, data e.g. ADD AL, data8
SUB SUB reg2/ mem, reg1/mem e.g. SUB reg2, reg1
SUB reg/mem, data e.g. SUB reg, data
SBB SBB reg2/ mem, reg1/mem e.g. SBB reg2, reg1
SBB reg/mem, data e.g. SBB reg, data
Arithmetic SBB A, data e.g. SBB AL, data8
Instructions
INC INC reg/ mem e.g. INC reg8

DEC DEC reg/ mem e.g. DEC mem

MUL MUL reg/ mem e.g. MUL reg

DIV DIV reg/ mem e.g. DIV reg

CMP CMP reg2/mem, reg1/ mem e.g. CMP reg2, reg1

21
LOGICAL INSTRUCTIONS:
Used to perform logical
operations.
Data Manipulation Instructions
⚫ Arithmetic Name Mnemonic
⚫ Logical & Bit Manipulation Increment INC
Decrement DEC
⚫ Shift Add ADD
Subtract SUB
Name Mnemonic Multiply MUL
Clear CLR Divide DIV
Complement COM Add with carry ADDC
AND AND Subtract with borrow SUBB
OR OR Negate NEG
Exclusive-OR XOR
Clear carry CLRC Name Mnemonic
Set carry SETC Logical shift right SHR
Complement carry COMC Logical shift left SHL
Enable interrupt EI Arithmetic shift right SHRA
Disable interrupt DI Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC
STRING MANIPULATION
INSTRUCTIONS:
String is a group of
bytes/words and their memory
is always allocated in
sequential order.
STRING INSTRUCTIONS:
MOVS/MOVSB/MOVSW
COMPS/COMPSB/COMPSW
INS/INSB/INSW
OUTS/OUTSB/OUTSW
SCAS/SCASB/SCASW
LODS/LODSB/LODSW
PROCESS CONTROL
INSTRUCTIONS:
Used to control the processor
action by setting /resetting the
flag values.
PROCESS CONTROL
INSTRUCTIONS:
STC
CLC
CMC
STD
CLD
STI
CLI
CONTROL TRANSFER
INSTRUCTIONS:
Used to transfer the branch
instructions during the
execution process.
CONTROL TRANSFER
INSTRUCTIONS:
CALL
RET
JUMP
Program Control(Control
Transfer) Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
ADDRESSING MODES IN 8086:
The different ways in which
address of the operand is
specified in an instruction is
called as addressing modes.
1.Immediate addressing mode
2.Direct addressing mode
3.Indirect addressing mode
4.Register addressing mode
5.Register indirect addressing
mode
6.Index addressing mode
7.Relative addressing mode
8.Autoincrement addressing
mode
 ADDRESSING MODES IN 8086
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
Basic Input/Output
Operations
Basic Input/Output Operations
⚫ We have seen instructions to:
⚫ Transfer information between the processor and the memory.

⚫ Perform arithmetic and logic operations

⚫ Program sequencing and flow control.

⚫ Input/Output operations which transfer data from the processor or

memory to and from the real world are essential.
⚫ In general, the rate of transfer from any input device to the
processor, or from the processor to any output device is likely to
the slower than the speed of a processor.
⚫ The difference in speed makes it necessary to create
mechanisms to synchronize the data transfer between them.

2
Basic Input/Output operations
(contd..)
⚫ Let us consider a simple task of reading a
character from a keyboard and displaying
that character on a display screen.
⚫ A simple way of performing the task is called
program-controlled I/O.
⚫ There are two separate blocks of instructions
in the I/O program that perform this task:
⚫ One block of instructions transfers the character into the processor.
⚫ Another block of instructions causes the character to be displayed.

3
 Basic Input/Output operations (contd..)
Bus

Processor
D ATAIN DATAOUT

SIN SOUT

K eyboard Display

Input:
•When a key is struck on the keyboard, an 8-bit character code is stored in the buffer
register DATAIN.
•A status control flag SIN is set to 1 to indicate that a valid character is in DATAIN.
•A program monitors SIN, and when SIN is set to 1, it reads the contents of DATAIN.
•When the character is transferred to the processor, SIN is automatically cleared.
•Initial state of SIN is 0.
4
Basic Input/Output operations (contd..)
Bus

Processor
D ATAIN DATAOUT

SIN SOUT

K eyboard Display

Output:
•When SOUT is equal to 1, the display is ready to receive a character.
•A program monitors SOUT, and when SOUT is set to 1, the processor transfers
a character code to the buffer DATAOUT.
•Transfer of a character code to DATAOUT clears SOUT to 0.
•Initial state of SOUT is 1.

5
Basic Input/Output operations
(contd..)
⚫ Buffer registers DATAIN and DATAOUT, and status flags SIN and SOUT
are part of a circuitry known as device interface.

⚫ To perform I/O transfers, we need machine instructions to:

⚫ Monitor the status of the status registers.

⚫ Transfer data among the I/O devices and the processor.

⚫ Instructions have similar format to the instructions used for moving data
between the processor and the memory.

⚫ How does the processor address the I/O devices?

⚫ Some memory address values may be used to refer to peripheral device
buffer registers such as DATAIN and DATAOUT.
⚫ This arrangement is called as Memory-Mapped I/O.
6
ASSEMBLY LANGUAGE
⚫ SOURCE PROGRAM- user program

⚫ OBJECT PROGRAM-assembled machine

language program.

⚫ ASSEMBLER:
⚫ Assembler translates the mneumonic into the
binary opcode that the computer
understands.
⚫ Ex:Add #5,(R2)
ASSEMBLER DIRECTIVES
ASSEMBLER DIRECTIVES ARE USED BY
THE ASSEMBLER TO TRANSLATE SOURCE
PROGRAM TO OBJECT PROGRAM.
ASSEMBLER DIRECTIVES
1.EQU – informs the assembler about the value
of the variable.
2.ORIGIN – tells the assembler program where
in the memory to place the data block that
follows.
3.DATAWORD – used to inform the assembler
of the data requirement
ASSEMBLER DIRECTIVES
4.RESERVE – used to reserve the memory
block
5.RETURN – identifies the point at which
execution of the program should be terminated
6.START – specifies the address of the location
at which the execution of the program to begin.
7.LOOP – indicates the beginning of the branch
instruction.
ASSEMBLY LANGUAGE
STATEMENT FORMAT
Label operation operand comment

Where
Label- name associated with memory address
where machine language instruction produced
from the statement will be loaded.
Operation-specified desired operation
Operand-specified operand