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 2ND EDITION

WRITE GRE AT CODE / VOLUME 1

UNDERSTANDING
THE MACHINE
R ANDALL HYDE
 PRAISE FOR THE FIRST EDITION OF
WRITE GREAT CODE, VOLUME 1

“Today’s programmers can hardly keep up with the race against inhumane
deadlines and new technologies; therefore, they rarely have a chance to learn
the basics of computer architectures and the inner workings of their program-
ming languages. This book fills in the gaps. I strongly recommend it.”
—InformIT.com

“[Write Great Code] isn’t your typical ‘teach yourself to program’ book. . .
It’s relevant to all languages, and all levels of programming experience. . .
Run, don’t walk, to buy and read this book.”
—Bay A rea L arge Installation S ystem A dministrators (BayLISA)

5/5 stars: “[Write Great Code] fills in the blanks nicely and really could be
part of a computer science degree required reading set. . . . Once this book
is read, you will have a greater understanding and appreciation for code that
is written efficiently—and you may just know enough to do that yourself. At
least you will have a great start at the art of crafting efficient software.”
—M acCompanion

“Great fun to read.”

—VSJ M agazine

“Write Great Code, Volume 1: Understanding the Machine should be on the

required reading list for anyone who wants to develop terrific code in any
language without having to learn assembly language.”
—WebServerTalk
 W R I T E G R E AT
CODE
VOLUME 1
2ND EDITION

Understanding the Machine

by Randall Hyde

San Francisco
WRITE GREAT CODE, Volume 1: Understanding the Machine, 2nd Edition.
Copyright © 2020 by Randall Hyde.

All rights reserved. No part of this work may be reproduced or transmitted in any form or by any means,
electronic or mechanical, including photocopying, recording, or by any information storage or retrieval
system, without the prior written permission of the copyright owner and the publisher.

ISBN-10: 1-71850-036-X
ISBN-13: 978-1-71850-036-5

Publisher: William Pollock

Executive Editor: Barbara Yien
Production Editor: Rachel Monaghan
Developmental Editor: Athabasca Witschi
Project Editor: Dapinder Dosanjh
Cover and Interior Design: Octopod Studios
Technical Reviewer: Anthony Tribelli
Copyeditor: Rachel Monaghan
Compositor: Danielle Foster
Proofreader: James Fraleigh
Illustrator: David Van Ness

For information on distribution, translations, or bulk sales, please contact No Starch Press, Inc. directly:
No Starch Press, Inc.
245 8th Street, San Francisco, CA 94103
phone: 1.415.863.9900; info@nostarch.com
www.nostarch.com

The Library of Congress issued the following Cataloging-in-Publication Data for the first edition of Volume 1:

Hyde, Randall.
Write great code : understanding the machine / Randall Hyde.
p. cm.
ISBN 1-59327-003-8
1. Computer programming. 2. Computer architecture. I. Title.
QA76.6.H94 2004
005.1--dc22
2003017502

No Starch Press and the No Starch Press logo are registered trademarks of No Starch Press, Inc. Other
product and company names mentioned herein may be the trademarks of their respective owners. Rather
than use a trademark symbol with every occurrence of a trademarked name, we are using the names only
in an editorial fashion and to the benefit of the trademark owner, with no intention of infringement of
the trademark.

The information in this book is distributed on an “As Is” basis, without warranty. While every precaution
has been taken in the preparation of this work, neither the author nor No Starch Press, Inc. shall have any
liability to any person or entity with respect to any loss or damage caused or alleged to be caused directly
or indirectly by the information contained in it.
About the Author
Randall Hyde is the author of The Art of Assembly Language and
Write Great Code, Volumes 1, 2, and 3 (all from No Starch Press), as
well as Using 6502 Assembly Language and P-Source (Datamost). He is
also the coauthor of Microsoft Macro Assembler 6.0 Bible (The Waite
Group). Over the past 40 years, Hyde has worked as an embedded
software/hardware engineer developing instrumentation for
nuclear reactors, traffic control systems, and other consumer elec-
tronics devices. He has also taught computer science at California
State Polytechnic University, Pomona, and at the University of
California, Riverside. His website is www.randallhyde.com/.

About the Technical Reviewer

Tony Tribelli has more than 35 years of experience in software
development, including work on embedded device kernels and
molecular modeling. He developed video games for 10 years
at Blizzard Entertainment. He is currently a software develop-
ment consultant and privately develops applications utilizing
computer vision.
 BRIEF CONTENTS

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Chapter 1: What You Need to Know to Write Great Code . . . . . . . . . . . . . . . . . . . . . . 1

Chapter 2: Numeric Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3: Binary Arithmetic and Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chapter 4: Floating-Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Chapter 5: Character Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Chapter 6: Memory Organization and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Chapter 7: Composite Data Types and Memory Objects . . . . . . . . . . . . . . . . . . . . . . 159

Chapter 8: Boolean Logic and Digital Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Chapter 9: CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Chapter 10: Instruction Set Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Chapter 11: Memory Architecture and Organization . . . . . . . . . . . . . . . . . . . . . . . . 319

Chapter 12: Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Chapter 13: Computer Peripheral Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Chapter 14: Mass Storage Devices and Filesystems . . . . . . . . . . . . . . . . . . . . . . . . . 381

Chapter 15: Miscellaneous Input and Output Devices . . . . . . . . . . . . . . . . . . . . . . . . 413

Afterword: Thinking Low-Level, Writing High-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Appendix A: ASCII Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
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 CONTE NT S IN DE TA IL

ACKNOWLEDGMENTS XVII

1
WHAT YOU NEED TO KNOW TO WRITE GREAT CODE 1
1.1 The Write Great Code Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 What This Book Covers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Assumptions This Book Makes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Characteristics of Great Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 The Environment for This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Additional Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2
NUMERIC REPRESENTATION 9
2.1 What Is a Number? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Numbering Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 The Decimal Positional Numbering System . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Radix (Base) Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 The Binary Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.4 The Hexadecimal Numbering System . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.5 The Octal Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Numeric/String Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Internal Numeric Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Bit Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Signed and Unsigned Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6 Useful Properties of Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Sign Extension, Zero Extension, and Contraction . . . . . . . . . . . . . . . . . . . . . . . . 26
2.8 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9 Binary-Coded Decimal Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.10 Fixed-Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.11 Scaled Numeric Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.12 Rational Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.13 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3
BINARY ARITHMETIC AND BIT OPERATIONS 37
3.1 Arithmetic Operations on Binary and Hexadecimal Numbers . . . . . . . . . . . . . . . . 37
3.1.1 Adding Binary Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.2 Subtracting Binary Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.3 Multiplying Binary Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.4 Dividing Binary Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Logical Operations on Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 Logical Operations on Binary Numbers and Bit Strings . . . . . . . . . . . . . . . . . . . . 44
3.4 Useful Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.1 Testing Bits in a Bit String Using AND . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.2 Testing a Set of Bits for Zero/Not Zero Using AND . . . . . . . . . . . . . . . 45
3.4.3 Comparing a Set of Bits Within a Binary String . . . . . . . . . . . . . . . . . 46
3.4.4 Creating Modulo-n Counters Using AND . . . . . . . . . . . . . . . . . . . . . . 47
3.5 Shifts and Rotates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 Bit Fields and Packed Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7 Packing and Unpacking Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.8 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4
FLOATING-POINT REPRESENTATION 61
4.1 Introduction to Floating-Point Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 IEEE Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2.1 Single-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2.2 Double-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.3 Extended-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . 69
4.2.4 Quad-Precision Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3 Normalization and Denormalized Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.4 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.5 Special Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6 Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.7 Floating-Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.7.1 Floating-Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.7.2 Floating-Point Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . 75
4.7.3 Floating-Point Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . 86
4.8 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5
CHARACTER REPRESENTATION 95
5.1 Character Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.1 The ASCII Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.2 The EBCDIC Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.1.3 Double-Byte Character Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1.4 The Unicode Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.5 Unicode Code Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.6 Unicode Code Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.7 Surrogate Code Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.8 Glyphs, Characters, and Grapheme Clusters . . . . . . . . . . . . . . . . . . 103
5.1.9 Unicode Normals and Canonical Equivalence . . . . . . . . . . . . . . . . . 105
5.1.10 Unicode Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1.11 Unicode Combining Characters . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.2 Character Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.1 Character String Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.2 Types of Strings: Static, Pseudo-Dynamic, and Dynamic . . . . . . . . . . . 116
5.2.3 Reference Counting for Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.2.4 Delphi Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.2.5 Custom String Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

x   
5.3 Character Set Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.1 Powerset Representation of Character Sets . . . . . . . . . . . . . . . . . . . . 119
5.3.2 List Representation of Character Sets . . . . . . . . . . . . . . . . . . . . . . . . 120
5.4 Designing Your Own Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.4.1 Designing an Efficient Character Set . . . . . . . . . . . . . . . . . . . . . . . . 122
5.4.2 Grouping the Character Codes for Numeric Digits . . . . . . . . . . . . . . 123
5.4.3 Grouping Alphabetic Characters . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.4.4 Comparing Alphabetic Characters . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.4.5 Grouping Other Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.5 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6
MEMORY ORGANIZATION AND ACCESS 131
6.1 The Basic System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.1.1 The System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.2 Physical Organization of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2.1 8-Bit Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2.2 16-Bit Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.2.3 32-Bit Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.2.4 64-Bit Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.2.5 Small Accesses on Non-80x86 Processors . . . . . . . . . . . . . . . . . . . . 141
6.3 Big-Endian vs. Little-Endian Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.4 The System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.4.1 Memory Access and the System Clock . . . . . . . . . . . . . . . . . . . . . . . 148
6.4.2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.4.3 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.5 CPU Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.5.1 The Direct Memory Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . 155
6.5.2 The Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.5.3 The Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.5.4 The Scaled-Index Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 157
6.6 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

7
COMPOSITE DATA TYPES AND MEMORY OBJECTS 159
7.1 Pointer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.1.1 Pointer Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.1.2 Pointers and Dynamic Memory Allocation . . . . . . . . . . . . . . . . . . . . 161
7.1.3 Pointer Operations and Pointer Arithmetic . . . . . . . . . . . . . . . . . . . . 162
7.2 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
7.2.1 Array Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.2.2 Array Representation in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.2.3 Accessing Elements of an Array . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
7.2.4 Multidimensional Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.3 Records/Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.3.1 Records in Pascal/Delphi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.3.2 Records in C/C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.3.3 Records in HLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.3.4 Records (Tuples) in Swift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.3.5 Memory Storage of Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

   xi
7.4 Discriminant Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.4.1 Unions in C/C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.4.2 Unions in Pascal/Delphi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.4.3 Unions in Swift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.4.4 Unions in HLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.4.5 Memory Storage of Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.4.6 Other Uses of Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.5 Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.5.1 Inheritance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.5.2 Class Constructors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.5.3 Polymorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.5.4 Abstract Methods and Abstract Base Classes . . . . . . . . . . . . . . . . . . 202
7.6 Classes in C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.6.1 Abstract Member Functions and Classes in C++ . . . . . . . . . . . . . . . . 206
7.6.2 Multiple Inheritance in C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.7 Classes in Java . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.8 Classes in Swift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.9 Protocols and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.10 Generics and Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.11 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

8
BOOLEAN LOGIC AND DIGITAL DESIGN 217
8.1 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.1.1 The Boolean Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.1.2 Boolean Postulates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.1.3 Boolean Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.2 Boolean Functions and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3 Function Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.4 Algebraic Manipulation of Boolean Expressions . . . . . . . . . . . . . . . . . . . . . . . . 223
8.5 Canonical Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8.5.1 Sum-of-Minterms Canonical Form and Truth Tables . . . . . . . . . . . . . . 225
8.5.2 Algebraically Derived Sum-of-Minterms Canonical Form . . . . . . . . . . 227
8.5.3 Product-of-Maxterms Canonical Form . . . . . . . . . . . . . . . . . . . . . . . . 228
8.6 Simplification of Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.7 What Does This Have to Do with Computers, Anyway? . . . . . . . . . . . . . . . . . . . 237
8.7.1 Correspondence Between Electronic Circuits and Boolean Functions . . 238
8.7.2 Combinatorial Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.7.3 Sequential and Clocked Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
8.8 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

9
CPU ARCHITECTURE 251
9.1 Basic CPU Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
9.2 Decoding and Executing Instructions: Random Logic vs. Microcode . . . . . . . . . . . 254
9.3 Executing Instructions, Step by Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
9.3.1 The mov Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9.3.2 The add Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

xii   
 9.3.3 The jnz Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
9.3.4 The loop Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.4 RISC vs. CISC: Improving Performance by Executing More, Faster, Instructions . . . 259
9.5 Parallelism: The Key to Faster Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
9.5.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
9.5.2 The Prefetch Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.5.3 Conditions That Hinder the Performance of the Prefetch Queue . . . . . . 267
9.5.4 Pipelining: Overlapping the Execution of Multiple Instructions . . . . . . . 267
9.5.5 Instruction Caches: Providing Multiple Paths to Memory . . . . . . . . . . . 272
9.5.6 Pipeline Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.5.7 Superscalar Operation: Executing Instructions in Parallel . . . . . . . . . . 275
9.5.8 Out-of-Order Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.5.9 Register Renaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.5.10 VLIW Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.5.11 Parallel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
9.5.12 Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
9.6 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

10
INSTRUCTION SET ARCHITECTURE 283
10.1 The Importance of Instruction Set Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
10.2 Basic Instruction Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
10.2.1 Choosing Opcode Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
10.2.2 Planning for the Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.2.3 Choosing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.2.4 Assigning Opcodes to Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.3 The Y86 Hypothetical Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.3.1 Y86 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.3.2 Y86 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.3.3 Operand Types and Addressing Modes on the Y86 . . . . . . . . . . . . 293
10.3.4 Encoding Y86 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.3.5 Examples of Encoding Y86 Instructions . . . . . . . . . . . . . . . . . . . . . 296
10.3.6 Extending the Y86 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . 300
10.4 Encoding 80x86 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.4.1 Encoding Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.4.2 Encoding the add Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
10.4.3 Encoding Immediate (Constant) Operands on the x86 . . . . . . . . . . . 314
10.4.4 Encoding 8-, 16-, and 32-Bit Operands . . . . . . . . . . . . . . . . . . . . . 315
10.4.5 Encoding 64-Bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.4.6 Alternate Encodings for Instructions . . . . . . . . . . . . . . . . . . . . . . . . 316
10.5 Implications of Instruction Set Design to the Programmer . . . . . . . . . . . . . . . . . 317
10.6 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

11
MEMORY ARCHITECTURE AND ORGANIZATION 319
11.1 The Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
11.2 How the Memory Hierarchy Operates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
11.3 Relative Performance of Memory Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . 324

   xiii
11.4 Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
11.4.1 Direct-Mapped Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
11.4.2 Fully Associative Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
11.4.3 n-Way Set Associative Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
11.4.4 Cache-Line Replacement Policies . . . . . . . . . . . . . . . . . . . . . . . . . . 329
11.4.5 Cache Write Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
11.4.6 Cache Use and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
11.5 NUMA and Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
11.6 Virtual Memory, Memory Protection, and Paging . . . . . . . . . . . . . . . . . . . . . . 332
11.7 Writing Software That Is Cognizant of the Memory Hierarchy . . . . . . . . . . . . . 336
11.8 Runtime Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
11.8.1 Static and Dynamic Objects, Binding, and Lifetime . . . . . . . . . . . . . 339
11.8.2 The Code, Read-Only, and Constant Sections . . . . . . . . . . . . . . . . . 340
11.8.3 The Static Variables Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
11.8.4 The Storage Variables Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
11.8.5 The Stack Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
11.8.6 The Heap Section and Dynamic Memory Allocation . . . . . . . . . . . . 342
11.9 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

12
INPUT AND OUTPUT 349
12.1 Connecting a CPU to the Outside World . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
12.2 Other Ways to Connect Ports to the System . . . . . . . . . . . . . . . . . . . . . . . . . . 353
12.3 I/O Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
12.3.1 Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
12.3.2 I/O-Mapped Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
12.3.3 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
12.4 I/O Speed Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
12.5 System Buses and Data Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.5.1 Performance of the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
12.5.2 Performance of the ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
12.5.3 The AGP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
12.6 Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
12.7 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
12.8 Timeouts on an I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.9 Interrupts and Polled I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
12.10 Protected-Mode Operation and Device Drivers . . . . . . . . . . . . . . . . . . . . . . . 364
12.10.1 The Device Driver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
12.10.2 Communication with Device Drivers . . . . . . . . . . . . . . . . . . . . . . 365
12.11 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

13
COMPUTER PERIPHERAL BUSES 367
13.1 The Small Computer System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.1.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
13.1.2 Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
13.1.3 SCSI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
13.1.4 SCSI Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

xiv   
13.2 The IDE/ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
13.2.1 The SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
13.2.2 Fibre Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
13.3 The Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
13.3.1 USB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
13.3.2 USB Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
13.3.3 Types of USB Transmissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
13.3.4 USB-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
13.3.5 USB Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
13.4 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

14
MASS STORAGE DEVICES AND FILESYSTEMS 381
14.1 Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.1.1 Floppy Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.1.2 Hard Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.1.3 RAID Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
14.1.4 Optical Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
14.1.5 CD, DVD, and Blu-ray Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
14.2 Tape Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
14.3 Flash Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
14.4 RAM Disks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
14.5 Solid-State Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
14.6 Hybrid Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.7 Filesystems on Mass Storage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.7.1 Sequential Filesystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.7.2 Efficient File Allocation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.8 Writing Software That Manipulates Data on a Mass Storage Device . . . . . . . . . 407
14.8.1 File Access Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
14.8.2 Synchronous and Asynchronous I/O . . . . . . . . . . . . . . . . . . . . . . . 409
14.8.3 The Implications of I/O Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
14.8.4 Memory-Mapped Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
14.9 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

15
MISCELLANEOUS INPUT AND OUTPUT DEVICES 413
15.1 Exploring Specific PC Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.1.1 The Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.1.2 The Standard PC Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
15.1.3 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.2 Mice, Trackpads, and Other Pointing Devices . . . . . . . . . . . . . . . . . . . . . . . . 417
15.3 Joysticks and Game Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.4 Sound Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.4.1 How Audio Interface Peripherals Produce Sound . . . . . . . . . . . . . . 420
15.4.2 The Audio and MIDI File Formats . . . . . . . . . . . . . . . . . . . . . . . . . 422
15.4.3 Programming Audio Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
15.5 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

   xv
AFTERWORD: THINKING LOW-LEVEL, WRITING HIGH-LEVEL 425

A
ASCII CHARACTER SET 427

GLOSSARY 431

INDEX 443

xvi   
 ACKNOWLEDGMENTS

Many people have read and reread every word, symbol, and punctuation
mark in this book in order to produce a better result. Kudos to the follow-
ing people for their careful work on the second edition: development editor
Athabasca Witschi, copyeditor/production editor Rachel Monaghan, and
proofreader James Fraleigh.
I would like to take the opportunity to graciously thank Anthony
Tribelli, a longtime friend, who went well beyond the call of duty when
doing a technical review of this book. He pulled every line of code out
of this book (including snippets) and compiled and ran it to make sure it
worked properly. His suggestions and opinions throughout the technical
review process have dramatically improved the quality of this work.
Of course, I would also like to thank all the countless readers over the
years who’ve emailed suggestions and corrections, many of which have
found their way into this second edition.

Thanks to all of you,

Randall Hyde
Visit https://textbookfull.com
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 1
W H AT YOU NE E D TO KNOW TO
W R IT E GR E AT CODE

The Write Great Code (WGC) series will teach

you how to write code you can be proud of;
code that will impress other programmers,
satisfy customers, and prove popular with
users; and code that people (customers, your boss,
and so on) won’t mind paying top dollar to obtain.
In general, the books in the WGC series will discuss how to write software
that achieves legendary status, eliciting the awe and admiration of other
programmers.

1.1 The Write Great Code Series

Write Great Code, Volume 1: Understanding the Machine (WGC1 hereafter) is the
first of six books in the WGC series. Writing great code requires a combina-
tion of knowledge, experience, and skill that programmers usually obtain
only after years of mistakes and discoveries. The purpose of this series is to
share with both new and experienced programmers a few decades’ worth of
 observations and experience. I hope that these books will help reduce the
time and frustration it takes to learn things “the hard way.”
This book, WGC1, fills in the low-level details that are often skimmed
over in a typical computer science or engineering curriculum. These details
are the foundation for the solutions to many problems, and you can’t write
efficient code without this information. Though I’m attempting to keep
each book independent, WGC1 might be considered a prerequisite for the
subsequent volumes in the series.
Write Great Code, Volume 2: Thinking Low-Level, Writing High-Level (WGC2)
immediately applies the knowledge from this book. WGC2 will teach you
how to analyze code written in a high-level language to determine the qual-
ity of the machine code that a compiler would generate for it. Optimizing
compilers don’t always generate the best machine code possible—the state-
ments and data structures you choose in your source files can have a big
impact on the efficiency of the compiler’s output. WGC2 will teach you how
to write efficient code without resorting to assembly language.
There are many attributes of great code besides efficiency, and the
third book in this series, Write Great Code, Volume 3: Engineering Software
(WGC3), will cover some of those. WGC3 will discuss software development
metaphors, development methologies, types of developers, system docu-
mentation, and the Unified Modeling Language (UML). WGC3 provides
the basis for personal software engineering.
Great code begins with a great design. Write Great Code, Volume 4:
Designing Great Code (WGC4), will describe the process of analysis and
design (both structured and object-oriented). WGC4 will teach you how to
translate an initial concept into a working design for your software systems.
Write Great Code, Volume 5: Great Coding (WGC5) will teach you how to
create source code that others can easily read and maintain, as well as how
to improve your productivity without the burden of the “busy work” that
many software engineering books discuss.
Great code works. Therefore, I’d be remiss not to include a book on test-
ing, debugging, and quality assurance. Few programmers properly test their
code. This generally isn’t because they find testing boring or beneath them,
but because they don’t know how to test their programs, eradicate defects,
and ensure the quality of their code. To help overcome this problem, Write
Great Code, Volume 6: Testing, Debugging, and Quality Assurance (WGC6) will
describe how to efficiently test your applications without all the drudgery
engineers normally associate with this task.

1.2 What This Book Covers

In order to write great code, you need to know how to write efficient code,
and to write efficient code, you must understand how computer systems
execute programs and how abstractions in programming languages map to
the low-level hardware capabilities of the machine.
In the past, learning great coding techniques has required learning
assembly language. While this isn’t a bad approach, it’s overkill. Learning

2   Chapter 1
assembly language involves learning two related subjects: machine organi-
zation, and programming in assembly language. The real benefits of learn-
ing assembly language come from the machine organization component.
Thus, this book focuses solely on machine organization so you can learn to
write great code without the overhead of also learning assembly language.
Machine organization is a subset of computer architecture that covers
low-level data types, internal CPU organization, memory organization and
access, low-level machine operations, mass storage organization, peripher-
als, and how computers communicate with the rest of the world. This book
concentrates on those parts of computer architecture and machine organi-
zation that are visible to the programmer or are helpful for understanding
why system architects chose a particular system design. The goal of learning
machine organization, and of this book, is not to enable you to design your
own CPU or computer system, but to equip you to make the most efficient
use of existing computer designs. Let’s do a quick run-through of the spe-
cific topics we’ll cover.
Chapters 2, 4, and 5 deal with basic computer data representation—
how computers represent signed and unsigned integer values, characters,
strings, character sets, real values, fractional values, and other numeric and
non-numeric quantities. Without a solid grasp of how computers represent
these various data types internally, it’ll be difficult for you to understand
why some operations that use these data types are so inefficient.
Chapter 3 discusses binary arithmetic and bit operations used by most
modern computer systems. It also offers several insights into how you can
write better code by using arithmetic and logical operations in ways not
normally taught in beginning programming courses. Learning these kinds
of standard “tricks” is part of how you become a great programmer.
Chapter 6 introduces memory, discussing how the computer accesses
its memory and describing characteristics of memory performance. This
chapter also covers various machine code addressing modes, which CPUs use
to access different types of data structures in memory. In modern applica-
tions, poor performance often occurs because the programmer, unaware of
the ramifications of memory access in their programs, creates bottlenecks.
Chapter 6 addresses many of these ramifications.
Chapter 7 returns to data types and representation by covering compos-
ite data types and memory objects: pointers, arrays, records, structures, and
unions. All too often, programmers use large composite data structures
without even considering the memory and performance impact of doing so.
The low-level description of these high-level composite data types will make
clear their inherent costs, so you can use them sparingly and wisely.
Chapter 8 discusses Boolean logic and digital design. This chapter
provides the mathematical and logical background you’ll need to under-
stand the design of CPUs and other computer system components. In par-
ticular, this chapter discusses how to optimize Boolean expressions, such
as those found in common high-level programming language statements
like if and while.

What You Need to Know to Write Great Code   3

 Continuing the hardware discussion from Chapter 8, Chapter 9 dis-
cusses CPU architecture. A basic understanding of CPU design and opera-
tion is essential if you want to write great code. By writing your code in a
manner consistent with how a CPU will execute it, you’ll get much better
performance using fewer system resources.
Chapter 10 discusses CPU instruction set architecture. Machine instruc-
tions are the primitive units of execution on any CPU, and the duration
of program execution is directly determined by the number and type of
machine instructions the CPU must process. Learning how computer archi-
tects design machine instructions can provide valuable insight into why cer-
tain operations take longer to execute than others. Once you understand the
limitations of machine instructions and how the CPU interprets them, you
can use this information to turn mediocre code sequences into great ones.
Chapter 11 returns to the subject of memory, covering memory archi-
tecture and organization. This chapter is especially important for anyone
wanting to write fast code. It describes the memory hierarchy and how to
maximize the use of the cache and other fast memory components. You’ll
learn about thrashing and how to avoid low-performance memory access in
your applications.
Chapters 12 through 15 describe how computer systems communicate
with the outside world. Many peripheral (input/output) devices oper-
ate at much lower speeds than the CPU and memory. You could write the
fastest-executing sequence of instructions possible, and your application
would still run slowly because you didn’t understand the limitations of the
I/O devices in your system. These four chapters discuss generic I/O ports,
system buses, buffering, handshaking, polling, and interrupts. They also
explain how to efficiently use many popular PC peripheral devices, includ-
ing keyboards, parallel (printer) ports, serial ports, disk drives, tape drives,
flash storage, SCSI, IDE/ATA, USB, and sound cards.

1.3 Assumptions This Book Makes

This book was written with certain assumptions about your prior knowl-
edge. You’ll reap the greatest benefit from this material if your skill set
matches the following:

• You should be reasonably competent in at least one modern program-

ming language. This includes C/C++, C#, Java, Swift, Python, Pascal/
Delphi (Object Pascal), BASIC, and assembly, as well as languages like
Ada, Modula-2, and FORTRAN.
• Given a small problem description, you should be capable of working
through the design and implementation of a software solution for that
problem. A typical semester or quarter course at a college or university
(or several months’ experience on your own) should be sufficient back-
ground for this book.

4   Chapter 1
 At the same time, this book is not language specific; its concepts tran-
scend whatever programming language(s) you’re using. Furthermore, this
book does not assume that you use or know any particular language. To
help make the examples more accessible, the programming examples rotate
among several languages. This book explains exactly how the example code
operates so that even if you’re unfamiliar with the specific programming
language, you’ll be able to understand its operation by reading the accom-
panying description.
This book uses the following languages and compilers in various examples:

• C/C++: GCC, Microsoft’s Visual C++

• Pascal: Embarcadero’s Delphi, Free Pascal
• Assembly language: Microsoft’s MASM, HLA (High-Level Assembly),
Gas (the Gnu Assembler; on the PowerPC and ARM)
• Swift 5 (Apple)
• Java (v6 or later)
• BASIC: Microsoft’s Visual Basic

Often, the examples appear in multiple languages, so it’s usually safe

to ignore a specific example if you don’t understand the syntax of the lan-
guage it uses.

1.4 Characteristics of Great Code

Different programmers will have different definitions for great code, so it’s
impossible to provide an all-encompassing definition that will satisfy every-
one. However, nearly everyone will agree that great code:

• Uses the CPU efficiently (that is, it’s fast)

• Uses memory efficiently (that is, it’s small)
• Uses system resources efficiently
• Is easy to read and maintain
• Follows a consistent set of style guidelines
• Uses an explicit design that follows established software engineering
conventions
• Is easy to enhance
• Is well tested and robust (that is, it works)
• Is well documented

We could easily add dozens of items to this list. Some programmers, for
example, may feel that great code must be portable, must follow a given set
of programming style guidelines, or must be written in a certain language
(or not be written in a certain language). Some may feel that great code
must be written as simply as possible, while others believe that it must be

What You Need to Know to Write Great Code   5

Random documents with unrelated
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 Ballater, view from Pannanich
spacious hotels with electric light and all modern conveniences on a
luxurious scale. Six miles distant is the famous Linn of Dee. The
Duke of Fife’s Highland residence, Mar Lodge, as well as Mar Castle
and Invercauld House, the home of the Farquharsons, are all in the
vicinity. From Braemar the ascent of Ben-Macdhui is usually made,
and sometimes also Loch-na-gar. A road leads from Braemar up the
valley of the Clunie and over the Cairnwell to Blairgowrie. (pp. 8, 21,
22, 33, 66, 68, 75, 112, 161, 162.)
=Byth= (360), usually New Byth, is a village three miles from
Cuminestown, and founded in 1764. It is a bare and treeless district.
Near it are the hills of Fishrie with a large number of crofts given off
by the Earl of Fife in 1830 to poor people evicted from other estates
at a time when the fashion began of amalgamating small holdings in
larger farms. (pp. 91, 124, 163.)
=Collieston= is a fishing village circling round a romantic bay near
the parish church of Slains. Here in 1588 one of the ships of the
Spanish Armada (_Santa Catherina_) was wrecked. The fishermen
still call the creek St Catherine’s Dub. Several small cannon have
been recovered from the pool. Eighty years ago, Collieston enjoyed
a certain notoriety for smuggling, and the graveyard of Slains close
by contains evidence of the deeds of violence that the contraband
trade brought about. (pp. 38, 48, 54.)
=Culter=, eight miles west of Aberdeen, celebrated for its paper-
mills, which date back to 1750. This paper-mill, the first of its kind in
the north, manufactured superfine paper and in particular the bank-
notes of the Aberdeen Bank. (p. 89.)
=Cuminestown= (466), a village on the north side of the Waggle Hill
in Monquhitter, was established by Joseph Cumine of Auchry in
1763. Joseph Cumine was a pioneer in agricultural improvement. He
planted trees and started the manufacture of linen. About a mile
distant is the smaller village of Garmond. The villages were once
much more populous in the days when the spinning of flax and the
knitting of stockings were rural industries. (p. 40.)
 Braemar from Craig Coynach
=Ellon= (1307), a thriving town on the Ythan, is the junction for the
Cruden and Boddam Railway. It has a shoe factory and large auction
marts for the sale of cattle. The Episcopal Church—St Mary’s on the
Rock—was designed by George Edmund Street and is a handsome
building in Early English style. A prominent divine in the pre-
Disruption controversies, Dr James Robertson, was parish minister
of Ellon from 1832 to 1843. Later he became a professor in
Edinburgh University. Ellon is a place of great antiquity. It was the
seat of jurisdiction of the Earldom of Buchan, and there the earls
held their Head Court. (pp. 29, 41, 163, 164, 171.)
=Fraserburgh= (10,570) is the third largest town in the county. It is a
busy, thriving place, being the great centre of the herring fishing
industry in Scotland. It was founded by Sir Alexander Fraser, one of
the Frasers of Philorth (now represented by Lord Saltoun). The
Frasers are said to have come into England with the Normans. A
royal charter was granted in 1546 erecting “Faithlie” as it was then
called into a free burgh of barony with all the privileges. Sir
Alexander Fraser was a great favourite with James VI and was
knighted at the baptism of Prince Henry, 1594: he was a man of
enterprise; he built the town and the harbour and erected public
buildings. He received from King James the privilege of founding a
University in Fraserburgh, and a building was set apart for this
institution. Not only so but a Principal was appointed in 1600. The
College may have been active for a few years, but very little is
known of its history. During the plague which raged for two years at
Aberdeen, the students of King’s College went for safety to
Fraserburgh in 1647 and, it is supposed, occupied the old College
buildings. A street in the town is still called “College Bounds.” (pp. 8,
38, 59, 61, 76, 94, 95, 101, 102, 163, 164, 169.)
The Doorway, Huntly Castle
 The Bass, Inverurie
=Huntly= (4229), the largest inland town of the county, is situated at
the confluence of the Deveron and the Bogie. It is the centre of an
extensive agricultural district—Strathbogie—and has woollen and
other manufactures. In the vicinity are the ruins of Huntly Castle, the
property of the Duke of Richmond and Gordon. The first Lords of
Strathbogie, being opposed to Bruce’s claims of kingship, were
disinherited and their lands bestowed on Sir Adam Gordon, whose
descendants became Earls of Huntly, Marquises of Huntly and
Dukes of Gordon. The old castle of Strathbogie was destroyed after
the battle of Glenlivet in 1594, but rebuilt as Huntly Castle in 1602.
Huntly is the birth-place of Dr George Macdonald, poet and novelist.
(pp. 29, 31, 91, 160, 162, 164, 176.)
=Insch= (616), a village on the Great North Railway, with Benachie
on one side, and the Culsalmond and Foudland Hills on the other.
The vitrified fort of Dunnideer is in the vicinity. (pp. 119, 164.)
=Inverurie= (4069), a royal burgh at the confluence of the Ury and
the Don. The workshops of the Great North of Scotland Railway
were removed from Kittybrewster to Inverurie some years ago,
thereby increasing the population of the burgh. It is one of the Elgin
parliamentary burghs. The Bass of Inverurie is a conical mound, long
considered artificial, but now ascertained to be a natural formation
due to the action of the two rivers. Inverurie has paper manufactures.
In the neighbourhood is Keith Hall, the seat of the Earl of Kintore.
(pp. 27, 71, 80, 108, 109, 113, 132, 137, 160, 162, 164, 165, 169.)
=Kemnay= (948), about five miles up Donside from Kintore, is well
known for its extensive granite quarries, which sent stones to build
the Forth Bridge and the Thames Embankment. Near it is Castle
Fraser, one of the finest inhabited castles of the county. Fetternear,
once the county seat of the bishops of Aberdeen, is on the opposite
side of the river. (p. 83.)
=Kintore= (818) is a royal burgh of great antiquity. A mile to the west
are the ruins of Hallforest, destroyed in 1639. Kintore has, in its
vicinity, several “Druidical” circles and sculptured stones. (pp. 27, 49,
108, 136, 160, 162, 164, 169.)
=Longside= (392) dates from 1801. A woollen factory brought for a
time prosperity to the village, but this has been given up and the
population dwindles. Rev. John Skinner, the author of
_Tullochgorum_, was for over sixty years minister of the Episcopal
Church at Linshart, close to the village of Longside. Here also was
born Jamie Fleeman, “the laird of Udny’s fool,” a half-witted person
whose blunt outspoken manner and shrewd remarks are still widely
remembered. (pp. 163, 176.)
=Maud= is the point where the Buchan railway bifurcates for
Peterhead and Fraserburgh. Maud is a centre for auction sales of
cattle. (p. 164.)
=Mintlaw= (377) was founded about the same period as Longside
and the fortunes of both villages, which are three miles apart, have
been similar. (p. 163.)
=Newburgh= (537), on the estuary of the Ythan, was at one time
notorious like Collieston for smuggling. Ships of small burden still
come up to its wharf at full tide and sometimes proceed as far as
Waterton. The bed of the estuary of the Ythan is covered with
mussels, much used in the past as bait by the local fishermen, as
well as for export to other fishing stations. The revenue from this
source has greatly fallen off in recent years—line-fishing having
suffered from the rise of trawling. (p. 48.)
=New Deer= (675) is a village established about 1805. Brucklay
Castle, the seat of the Dingwall-Fordyce family, recently converted
into a mansion of the old Scottish castellated style, and surrounded
with tasteful grounds, is now one of the most charming edifices in the
district. A mile to the west is the ruined castle of Fedderat. (p. 138.)
=New Pitsligo= (pa. 2226) is a village in the neighbourhood of the
sources of the Ugie, and extending for a mile in two parallel streets
along the eastern slope of the hill of Turlundie. It stands 500 feet
above sea-level. The village takes its name from Sir William Forbes
of Pitsligo, who founded it in 1787. Here a linen trade was at one
time carried on; this gave place to hand-loom weaving and ultimately
to lace-making. The Episcopal Church was designed by G. Edmund
Street, and it is said to be one of the best examples of his work in
Scotland. The manufacture of moss-litter from the peat in the
neighbourhood was recently started. (pp. 91, 163.)
=Old Deer= (179) is prettily situated on the South Ugie. The district
has memories of St Columba and St Drostan. In the neighbourhood
are the ruins of a Cistercian Abbey, and “Druidical” circles. (pp. 2,
105, 113, 115, 117, 123.)
=Old Meldrum= (1110) was erected by charter into a burgh of barony
in 1672. It is well known for its turnip-seed. It used to employ many
persons in handloom weaving and in the knitting of stockings. Both
industries have fallen to decay, and the population tends to dwindle.
There is a long-established distillery in the town. (pp. 108, 112, 163,
164.)
=Peterhead= (13,560), the most easterly town in Scotland, is built of
red granite. A century ago it was a fashionable watering-place, and
used to be a whaling station. Now its chief industry is the herring
fishing. South of the town a harbour of refuge is being constructed by
convict labour, from the convict prison close by. The harbour of
refuge will cost, it is said, a million of money and its construction will
occupy 25 to 30 years. A linen factory once existed here, as also a
woollen factory, which exported cloth to the value of £12,000 a year.
Both became extinct, but the woollen industry was revived and still
prospers. Another prominent industry is granite polishing. At
Inverugie Castle was born Field-Marshal James Keith, whose statue
stands in front of the Town-House. The “Pretender” landed at
Peterhead on Christmas Day, 1715. Peterhead was erected into a
burgh of barony in 1593 by Earl Marischal, the founder of Marischal
College, Aberdeen. It continued to be part of the Earl’s estates till the
rebellion of 1715, when the lands were confiscated. The Peterhead
portion is now the property of the Merchant Maiden Hospital of
Edinburgh. (pp. 8, 29, 38, 39, 41, 57, 66, 68, 76, 83, 94, 95, 101,
102, 111, 163, 164, 169, 171.)
=Rosehearty= (1308) is a misspelt Gaelic name of which _Ros_, a
promontory, and _ard_, a height, are undoubted elements. The little
town stands on the shore a mile north of Pitsligo[1]. There is a
tradition that in the fourteenth century a party of Danes landed and
took up residence here, instructing the inhabitants, who were mostly
crofters, in the art of fishing. (pp. 62, 162.)
 The White Horse on Mormond Hill

[1] Alexander Forbes, fourth and last Lord Pitsligo (1678-1762)

was a warm supporter of the exiled Stuarts and took part in both
rebellions. After Culloden, he remained in hiding, his chief place
of concealment being a cave in the rocks west of Rosehearty.
M. A.
=Strichen= (1094) was formerly called Mormond, from the hill at the
base of which the village stands. This hill owing to the comparatively
level character of the surrounding country is a conspicuous feature in
the landscape for miles. On the south-western side, the figure of a
horse is cut out in the turf, the space being filled up with white
stones. This “White Horse” occupies half an acre of ground and is
visible at a great distance. On the south side of the hill an antlered
stag on a larger scale is figured in the same manner. This was done
so late as 1870. (pp. 11, 16, 38, 91, 158.)
=Torphins= (455), a rising village on Deeside, much resorted to by
Aberdonians in the summer months. (p. 106.)
=Turriff= (2346) is situated on a table-land on the north of the burn of
Turriff near its junction with the Deveron. Turriff is midway between
Aberdeen and Elgin; hence the couplet—
Choose ye, choise ye, at the Cross o’ Turra
Either gang to Aberdeen or Elgin o’ Moray.
Turriff is very ancient, being mentioned in the _Book of Deer_, under
the name of Turbruad, as the seat of a Celtic monastery dedicated to
St Congan, a follower of St Columba. The double belfry of the old
church (date 1635) is really a piece of castellated architecture
applied to an ecclesiastical edifice. The churchyard gateway is also
Early Scottish Renaissance. (pp. 11, 31, 40, 110, 112, 119, 163,
164.)
Fig. 1. Area of Aberdeenshire compared with that of Scotland
Fig. 2. Population of Aberdeenshire compared with that of
Scotland
Fig. 3. Comparative density of Population to square mile
 Fig. 4. Proportion of cultivated and uncultivated areas in
Aberdeenshire—practically 50%
Fig. 5. Proportionate area of Crops in Aberdeenshire (1909)
Fig. 6. Proportionate area of Crops, Pasture and Woodlands in
Aberdeenshire (1909)
Fig. 7. Proportionate numbers of live-stock in Aberdeenshire
(1909)
Fig. 8. Quantity of Fish (all kinds) landed in Aberdeenshire as
compared with that of Scotland (1909), almost 50%
Fig. 9. Quantity of Herrings landed in Aberdeenshire as
compared with that of Scotland (1909)
Cambridge:
PRINTED BY JOHN CLAY, M.A.
AT THE UNIVERSITY PRESS
_The Cambridge University Press_
Click here for larger map
GEOLOGICAL MAP OF COUNTY OF
ABERDEEN
_Copyright. George Philip & Son Ltd._
Click here for larger map
 Transcriber’s Notes

Page 62—changed Pitullie to Pittullie

Page 119—changed possesssed to possessed
Page 148—changed Sreet to Street
Page 164—changed Kenmay to Kemnay
Page 164—changed Formartin to Formartine
Page 189—changed Glenlivat to Glenlivet
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