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Computers Software Engineering and Digital Devices
Richard C. Dorf Digital Instant Download
Author(s): Richard C. Dorf
ISBN(s): 9780849373404, 0849373409
Edition: Kindle
File Details: PDF, 4.78 MB
Year: 2005
Language: english
# 2006 by Taylor & Francis Group, LLC
 Preface

Purpose
The purpose of The Electrical Engineering Handbook, 3rd Edition is to provide a ready reference for the
practicing engineer in industry, government, and academia, as well as aid students of engineering. The third
edition has a new look and comprises six volumes including:
Circuits, Signals, and Speech and Image Processing
Electronics, Power Electronics, Optoelectronics, Microwaves, Electromagnetics, and Radar
Sensors, Nanoscience, Biomedical Engineering, and Instruments
Broadcasting and Optical Communication Technology
Computers, Software Engineering, and Digital Devices
Systems, Controls, Embedded Systems, Energy, and Machines
Each volume is edited by Richard C. Dorf, and is a comprehensive format that encompasses the many
aspects of electrical engineering with articles from internationally recognized contributors. The goal is to
provide the most up-to-date information in the classical fields of circuits, signal processing, electronics,
electromagnetic fields, energy devices, systems, and electrical effects and devices, while covering the emerging
fields of communications, nanotechnology, biometrics, digital devices, computer engineering, systems, and
biomedical engineering. In addition, a complete compendium of information regarding physical, chemical,
and materials data, as well as widely inclusive information on mathematics is included in each volume. Many
articles from this volume and the other five volumes have been completely revised or updated to fit the needs
of today and many new chapters have been added.
The purpose of this volume, Computers, Software Engineering, and Digital Devices, is to provide a ready
reference to subjects in the fields of digital and logical devices, displays, testing, software, and computers. Here
we provide the basic information for understanding these fields. We also provide information about the
emerging fields of programmable logic, hardware description languages, and parallel computing.

Organization
The information is organized into three sections. The first two sections encompass 20 chapters and the last
section summarizes the applicable mathematics, symbols, and physical constants.
Most articles include three important and useful categories: defining terms, references, and further infor-
mation. Defining terms are key definitions and the first occurrence of each term defined is indicated in boldface
in the text. The definitions of these terms are summarized as a list at the end of each chapter or article.
The references provide a list of useful books and articles for follow-up reading. Finally, further information
provides some general and useful sources of additional information on the topic.

Locating Your Topic

Numerous avenues of access to information are provided. A complete table of contents is presented at the
front of the book. In addition, an individual table of contents precedes each section. Finally, each chapter
begins with its own table of contents. The reader should look over these tables of contents to become familiar
with the structure, organization, and content of the book. For example, see Section II: Computer Engineering,

# 2006 by Taylor & Francis Group, LLC

then Chapter 17: Parallel Processors, and then Chapter 17.2: Parallel Computing. This tree-and-branch table
of contents enables the reader to move up the tree to locate information on the topic of interest.
Two indexes have been compiled to provide multiple means of accessing information: subject index and
index of contributing authors. The subject index can also be used to locate key definitions. The page on which
the definition appears for each key (defining) term is clearly identified in the subject index.
The Electrical Engineering Handbook, 3rd Edition is designed to provide answers to most inquiries and direct
the inquirer to further sources and references. We hope that this handbook will be referred to often and that
informational requirements will be satisfied effectively.

Acknowledgments
This handbook is testimony to the dedication of the Board of Advisors, the publishers, and my editorial
associates. I particularly wish to acknowledge at Taylor & Francis Nora Konopka, Publisher; Helena Redshaw,
Editorial Project Development Manager; and Richard Tressider, Project Editor. Finally, I am indebted to the
support of Elizabeth Spangenberger, Editorial Assistant.

Richard C. Dorf
Editor-in-Chief

# 2006 by Taylor & Francis Group, LLC

 Editor-in-Chief

Richard C. Dorf, Professor of Electrical and Computer Engineering at the University of California, Davis,
teaches graduate and undergraduate courses in electrical engineering in the fields of circuits and control
systems. He earned a Ph.D. in electrical engineering from the U.S. Naval Postgraduate School, an M.S. from
the University of Colorado, and a B.S. from Clarkson University. Highly concerned with the discipline of
electrical engineering and its wide value to social and economic needs, he has written and lectured
internationally on the contributions and advances in electrical engineering.
Professor Dorf has extensive experience with education and industry and is professionally active in the fields
of robotics, automation, electric circuits, and communications. He has served as a visiting professor at the
University of Edinburgh, Scotland; the Massachusetts Institute of Technology; Stanford University; and the
University of California, Berkeley.
Professor Dorf is Fellow of The Institute of Electrical and Electronics Engineers and a Fellow of the
American Society for Engineering Education. Dr. Dorf is widely known to the profession for his Modern
Control Systems, 10th Edition (Addison-Wesley, 2004) and The International Encyclopedia of Robotics (Wiley,
1988). Dr. Dorf is also the co-author of Circuits, Devices and Systems (with Ralph Smith), 5th Edition (Wiley,
1992), and Electric Circuits, 7th Edition (Wiley, 2006). He also is author of Technology Ventures (McGraw-
Hill, 2005) and The Engineering Handbook, 2nd Edition (CRC Press, 2005).

# 2006 by Taylor & Francis Group, LLC

# 2006 by Taylor & Francis Group, LLC
 Advisory Board

Frank Barnes William Kersting Richard S. Sandige

University of Colorado New Mexico State University California Polytechnic State
Boulder, Colorado Las Cruces, New Mexico University
San Luis Obispo, California
Joseph Bronzino
Trinity College Vojin Oklobdzia
Hartford, Connecticut University of California Leonard Shaw
Davis, California Polytechnic University
Wai-Kai Chen Brooklyn, New York
University of Illinois
Chicago, Illinois
John V. Oldfield John W. Steadman
Syracuse University
Delores Etter University of South Alabama
Syracuse, New York
United States Naval Academy Mobile, Alabama
Annapolis, Maryland

Lyle Feisel Banmali Rawat R. Lal Tummala

State University of New York University of Nevada Michigan State University
Binghamton, New York Reno, Nevada East Lansing, Michigan

# 2006 by Taylor & Francis Group, LLC

# 2006 by Taylor & Francis Group, LLC
 Contributors

M. Abdelguerfi James M. Feldman Paul C. Jorgensen

University of New Orleans Northeastern University Grand Valley State University
New Orleans, Louisiana Boston, Massachusetts Rockford, Michigan

Cajetan M. Akujuobi Tse-yun Feng Miro Kraetzl

Prairie View A&M University Pennsylvania State University Defence Science and Technology
Prairie View, Texas University Park, Pennsylvania Organisation
Salisbury, Australia
Carl A. Argila James F. Frenzel
Dhammika
Software Engineering Consultant University of Idaho
Kurumbalapitiya
Pico Rivera, California Moscow, Idaho Harvey Mudd College
Claremont, California
B.R. Bannister Raphael Finkel
University of Hull (retired) University of Kentucky Peter A. Lee
Hull, U.K. Lexington, Kentucky East of England Development Agency
Cambridge, U.K.
Bill D. Carroll James M. Gilbert
University of Texas University of Hull Young Choon Lee
Arlington, Texas Hull, U.K. University of Sydney
Sydney, Australia
Michael D. Ciletti Peter Graham
University of Colorado University of Minnesota Ted G. Lewis
Colorado Springs, Colorado Saint Paul, Minnesota Naval Postgraduate School
Monterey, California
George A. Constantinides Chris G. Guy
Imperial College of Science University of Reading Albert A. Liddicoat
London, U.K. Reading, U.K. California Polytechnic State University
San Luis Obispo, California
J. Arlin Cooper Carl Hamacher
Sandia National Laboratories Queen’s University
Jay Liebowitz
Johns Hopkins University
Albuquerque, New Mexico Kingston, Canada
Rockville, Maryland
Edward W. Czeck H.S. Hinton
M. Mansuripur
Chrysatis Symbolic Design Utah State University
University of Arizona
North Billerica, Massachusetts Logan, Utah Tucson, Arizona

Bulent I. Dervisoglu Barry W. Johnson Johannes J. Martin

Silicon Graphics, Inc. University of Virginia University of New Orleans
Mountain View, California Charlottesville, Virginia New Orleans, Louisiana

R. Eskicioglu Anna M. Johnston James E. Morris

University of Alberta Sandia National Laboratories Portland State University
Edmonton, Canada Albuquerque, New Mexico Lake Oswego, Oregon

# 2006 by Taylor & Francis Group, LLC

Gregory L. Moss Michaela Serra Zvonko Vranesic
Purdue University University of Victoria University of Toronto
West Lafayette, Indiana Victoria, Canada Toronto, Canada

Franco P. Preparata Mostafa Hashem Sherif Larry F. Weber

Brown University AT&T The Society for Information
Providence, Rhode Island Tinton Falls, New Jersey Highland, New York

W. David Pricer Solomon Sherr D.G. Whitehead

Pricer Business Services Westland Electronics University of Hull
Charlotte, Vermont Old Chatham, New York Hull, U.K.

Jacques Raymond Lynne A. Slivovsky Phillip J. Windley

University of Ottawa California Polytechnic State University Brigham Young University
Ottawa, Canada San Luis Obispo, California Provo, Utah

Evelyn P. Rozanski John Staudhammer S.N. Yanushkevich

Rochester Institute of Technology University of Florida University of Calgary
Rochester, New York Gainesville, Florida Calgary, Canada

Matthew N.O. Sadiku Ronald J. Tallarida Safwat Zaky

Prairie View A&M University Temple University University of Toronto
Prairie View, Texas Philadelphia, Pennsylvania Toronto, Canada

Richard S. Sandige Charles W. Therrien Albert Y. Zomaya

California Polytechnic State University Naval Postgraduate School University of Sydney
San Luis Obispo, California Monterey, California Sydney, Australia

Nan C. Schaller Richard F. Tinder

Rochester Institute of Technology Washington State University
Rochester Center, New York Pullman, Washington

# 2006 by Taylor & Francis Group, LLC

 Contents

SECTION I Digital Devices

1 Logic Elements
1.1 IC Logic Family Operation and Characteristics Gregory L. Moss
1.2 Logic Gates (IC) Peter Graham
1.3 Bistable Devices Richard S. Sandige and Lynne A. Slivovsky
1.4 Optical Devices H.S. Hinton

2 Memory Devices
2.1 Integrated Circuits (RAM, ROM) W. David Pricer
2.2 Magnetic Tape Peter A. Lee
2.3 Magneto-Optical Disk Data Storage M. Mansuripur

3 Logical Devices
3.1 Combinational Networks and Switching Algebra Franco P. Preparata
3.2 Logic Circuits Richard S. Sandige and Albert A. Liddicoat
3.3 Registers and Their Applications B.R. Bannister, D.G. Whitehead,
and James M. Gilbert
3.4 Programmable Arrays George A. Constantinides
3.5 Arithmetic Logic Units Bill D. Carroll
3.6 Programmable Logic Albert A. Liddicoat and Lynne A. Slivovsky

4 Microprocessors
4.1 Practical Microprocessors John Staudhammer
4.2 Applications Phillip J. Windley and James F. Frenzel

5 Displays
5.1 Light-Emitting Diodes James E. Morris
5.2 Liquid-Crystal Displays James E. Morris
5.3 Plasma Displays Larry F. Weber

6 Data Acquisition Dhammika Kurumbalapitiya

7 Testing
7.1 Digital IC Testing Michaela Serra
7.2 Design for Test Bulent I. Dervisoglu

# 2006 by Taylor & Francis Group, LLC

SECTION II Computer Engineering

8 Organization
8.1 Number Systems Richard F. Tinder
8.2 Computer Arithmetic S.N. Yanushkevich
8.3 Architecture Carl Hamacher, Zvonko Vranesic, and Safwat Zaky
8.4 Microprogramming Jacques Raymond

9 Programming
9.1 Assembly Language James M. Feldman and Edward W. Czeck
9.2 High-Level Languages Ted G. Lewis
9.3 Data Types and Data Structures Johannes J. Martin
9.4 The Use of Hardware Description Languages in Computer Design Michael D. Ciletti

10 Input and Output Solomon Sherr

11 Secure Electronic Commerce Mostafa Hashem Sherif

12 Software Engineering
12.1 Tools and Techniques Carl A. Argila
12.2 Software Testing Paul C. Jorgensen

13 Computer Graphics Nan C. Schaller and Evelyn P. Rozanski

14 Computer Networks Matthew N.O. Sadiku and Cajetan M. Akujuobi

15 Fault Tolerance Barry W. Johnson

16 Knowledge Engineering
16.1 Databases M. Abdelguerfi and R. Eskicioglu
16.2 Rule-Based Expert Systems Jay Liebowitz

17 Parallel Processors
17.1 Parallel Processors Tse-yun Feng and Miro Kraetzl
17.2 Parallel Computing Young Choon Lee and Albert Y. Zomaya

18 Operating Systems Raphael Finkel

19 Computer and Communications Security J. Arlin Cooper and Anna M. Johnston

20 Computer Reliability Chris G. Guy

SECTION III Mathematics, Symbols, and Physical Constants

Introduction Ronald J. Tallarida

Greek Alphabet
International System of Units (SI)

# 2006 by Taylor & Francis Group, LLC

 Conversion Constants and Multipliers
Physical Constants
Symbols and Terminology for Physical and Chemical Quantities
Credits
Probability for Electrical and Computer Engineers Charles W. Therrien

Indexes
Author Index

Subject Index

# 2006 by Taylor & Francis Group, LLC

 I
Digital Devices
1 Logic Elements G.L. Moss, P. Graham, R.S. Sandige, L.A. Slivovsky, H.S. Hinton
IC Logic Family Operation and Characteristics *
Logic Gates (IC) *
Bistable Devices *

Optical Devices

2 Memory Devices W.D. Pricer, P.A. Lee, M. Mansuripur

Integrated Circuits (RAM, ROM) *
Magnetic Tape *
Magneto-Optical Disk Data Storage

3 Logical Devices F.P. Preparata, R.S. Sandige, A.A. Liddicoat,

B.R. Bannister, D.G. Whitehead, J.M. Gilbert, G.A. Constantinides,
B.D. Carroll, L.A. Slivovsky
Combinational Networks and Switching Algebra Logic Circuits Registers and Their
* *

Applications Programmable Arrays Arithmetic Logic Units Programmable Logic

* * *

4 Microprocessors J. Staudhammer, P.J. Windley, J.F. Frenzel

Practical Microprocessors *
Applications

5 Displays J.E. Morris, L.F. Weber

Light-Emitting Diodes *
Liquid-Crystal Displays *
Plasma Displays

6 Data Acquisition D. Kurumbalapitiya

Introduction The Analog and Digital Signal Interface Analog Signal Conditioning
* * *

Sample-and-Hold and A/D Techniques in Data Acquisition The Communication Interface of a

*

Data Acquisition System Data Recording Software Aspects

* *

7 Testing M. Serra, B.I. Dervisoglu

Digital IC Testing *
Design for Test

# 2006 by Taylor & Francis Group, LLC

 1
Logic Elements
Gregory L. Moss
Purdue University 1.1 IC Logic Family Operation and Characteristics
Peter Graham IC Logic Families and Subfamilies TTL Logic Family CMOS
* *

University of Minnesota Logic Family ECL Logic Family Logic Family Circuit
* *

Parameters Interfacing between Logic Families

*

Richard S. Sandige
1.2 Logic Gates (IC)
California Polytechnic State
Gate Specification Parameters Bipolar Transistor Gates
* *

University
Complementary Metal-Oxide Semiconductor (CMOS) Logic *

Lynne A. Slivovsky CMOS Design Considerations Choosing a Logic Family

*

California Polytechnic State 1.3 Bistable Devices

University Latches Flip-Flops
*

H.S. Hinton 1.4 Optical Devices

Utah State University All-Optical Devices Optoelectronic Devices
*

1.1 IC Logic Family Operation and Characteristics

Gregory L. Moss
Digital logic circuits can be classified as belonging to one of two categories, either combinational (also called
combinatorial) or sequential logic circuits. The output logic level of a combinational circuit depends only on
the current logic levels at the circuit’s inputs. Conversely, sequential logic circuits have a memory
characteristic, making the sequential circuit’s output dependent not only on current input conditions but also
on the current output state of the circuit. The primary building block of combinational circuits is the
logic gate. The three simplest logic gate functions are the inverter (or NOT), AND and OR. Other basic logic
functions are derived from these three. See Table 1.1 for truth table definitions of the various types of logic
gates. The memory elements used to construct sequential logic circuits are called latches and flip-flops.
The integrated circuit switching logic used in modern digital systems generally comes from one of three
families: transistor-transistor logic (TTL), complementary metal oxide semiconductor logic (CMOS) or
emitter coupled logic (ECL). Each logic family has its advantages and disadvantages. The three major families
are divided into various subfamilies derived from performance improvements in IC design technology. Bipolar
transistors provide switching action in both the TTL and ECL families, while enhancement-mode MOS
transistors form the basis for the CMOS family. Recent improvements in switching-circuit performance are
also attained using BiCMOS technology, the merging of bipolar and CMOS technologies on a single chip.
A particular logic family is usually selected by digital designers based on criteria such as:
1. Switching speed
2. Power dissipation
3. PC board-area requirements (level of integration)
4. Output drive capability (fan-out)
5. Noise immunity characteristics
6. Product breadth
7. Sourcing of components

# 2006 by Taylor & Francis Group, LLC

TABLE 1.1 Defining Truth Tables for Logic Gates
1-Input Function 2-Input Functions

Input Output Inputs Output Functions

A NOT A B AND OR NAND NOR XOR XNOR

0 1 0 0 0 0 1 1 0 1
1 0 0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1

IC Logic Families and Subfamilies

Integrated circuit logic families actually consist of several subfamilies of ICs that differ in performance
characteristics. The TTL logic family has been the most widely used family type for applications employing small
scale integration (SSI) or medium scale integration (MSI) integrated circuits. Lower power consumption and
higher levels of integration are the principal advantages of the CMOS family. The ECL family is generally used in
applications requiring high-speed switching logic. Today, the most common device-numbering system used in
the TTL and CMOS families has a prefix of 54 (generally used in military applications and having an operating
temperature range from 55 to 125–C) and 74 (generally used in industrial/commercial applications and having
an operating temperature range from 0 to 70–C). Table 1.2 identifies various logic families and subfamilies.

TTL Logic Family

The TTL family has been the most widely used logic family for many years in applications employing SSI and
MSI. It is moderately fast and offers a great variety of standard chips, but it is a mature technology that is
generally no longer used in new circuit designs.

TABLE 1.2 Logic Families and Subfamilies

Family (Subfamily) Description

TTL Transistor-Transistor Logic

74xx Standard TTL
74Lxx Low power TTL
74Hxx High speed TTL
74Sxx Schottky TTL
74LSxx Low power Schottky TTL
74Asxx Advanced Schottky TTL
74ALSxx Advanced low power Schottky TTL
74Fxx Fast TTL
CMOS Complementary Metal Oxide Semiconductor
4xxx Standard CMOS
74Cxx Standard CMOS using TTL numbering system
74HCxx High speed CMOS
74HCTxx High speed CMOS – TTL compatible
74FCTxx Fast CMOS – TTL compatible
74Acxx Advanced CMOS
74ACTxx Advanced CMOS – TTL compatible
74AHCxx Advanced high speed CMOS
74AHCTxx Advanced high speed CMOS – TTL compatible
ECL (or CML) Emitter Coupled (Current Mode) Logic
10xxx Standard ECL
10Hxxx High speed ECL

# 2006 by Taylor & Francis Group, LLC

 The active switching element used in all TTL family circuits is the NPN (not pointing in) bipolar junction
transistor (BJT). The transistor is turned on when the base is approximately 0.7 volts more positive than the
emitter and there is a sufficient flow of base current. The turned-on transistor (in non-Schottky subfamilies) is
said to be in saturation and, ideally, acts like a closed switch between collector and emitter terminals. The
transistor is turned off when the base is not biased with a high enough voltage with respect to the emitter. In
this condition, the transistor acts like an open switch between the collector and emitter terminals.
Figure 1.1 illustrates the transistor circuit blocks used in a standard TTL inverter. Four transistors are used
to achieve the inverter function. The gate input connects to the emitter of transistor Q1, the input-coupling
transistor. A clamping diode on the input prevents negative input-voltage spikes from damaging Q1. The
collector voltage (and current) of Q1 controls Q2, the phase-splitter transistor. Q2 in turn controls the Q3 and
Q4 transistors, forming the output circuit called a totem-pole arrangement. Q4 serves as a pull-up transistor,
pulling the output high when it is turned on. Q3 does the opposite to the output, acting as a pull-down
transistor. Q3 pulls the output low when it is turned on. Only one of the two transistors in the totem pole can
be turned on at a time. This is the function of the phase-splitter transistor.
When a high-logic level is applied to the inverter’s input, Q1’s base-emitter junction will be reverse-biased
and the base-collector junction will be forward-biased. This circuit condition will allow Q1 collector current
to flow into the base of Q2, saturating Q2 and providing base current into Q3, and turning on Q3 as well.

V
CC

VB4 pull-up
(to VCC)
VC2 Q4

VE1 input VC1 VB2 phase- VE4

input coupling splitter output
Q1 Q2 VC3
VE2 VB3 pull-down
(to GND)
Q3

VCC

R4
R1 R2

Q4
Q1
D2
input Q2
output
D1 Q3
R3

input VC1 Q2 VC2 VE2 Q3 VC3 Q4 VE4 output

hi hi on low hi on low off open low

low low off hi low off open on hi hi

FIGURE 1.1 TTL inverter circuit and operation.

# 2006 by Taylor & Francis Group, LLC

The collector voltage of Q2 is too low to turn on Q4, so that it appears as an opening in the top part of the
totem pole. A diode between the two totem-pole transistors provides an extra voltage drop, in series with
the base-emitter junction of Q4, to ensure that Q4 will be turned off when Q2 is turned on. The saturated Q3
transistor brings the output near ground potential, producing a low-output result for a high input into the
inverter.
When a low logic level is applied to the inverter’s input, Q1’s base-emitter junction will be forward-biased
and the base-collector junction will be reverse-biased. This circuit condition will turn on Q1, shorting the
collector terminal to the emitter and, therefore, to ground (low-level). This low voltage also acts on the base of
Q2 and turns Q2 off. With Q2 off, insufficient base current flows into Q3, turning it off also. The Q2 leakage
current is shunted to ground with a resistor to prevent the partial turning on of Q3. The collector voltage of
Q2 is pulled to a high potential with another resistor and then turns on Q4, making it appear as a short in the
top of the totem pole. The saturated Q4 transistor provides a low-resistance path from VCC to the output,
producing high output for a low input into the inverter.
A TTL NAND gate is similar to the inverter circuit. The only exception is that the input-coupling transistor
Q1 is constructed with multiple emitter-base junctions and each input to the NAND is connected to a separate
emitter terminal. Any of the transistor’s multiple emitters can turn on Q1. The TTL NAND gate thus functions
in the same manner as the inverter, in that if any of the NAND gate inputs are low, the same circuit action will
take place as with a low input to the inverter. Therefore, any time a low input is applied to the NAND gate, it
will produce high output. Only if all the NAND gate inputs are simultaneously high, will it produce the same
circuit action as the inverter, with its single input high and the resultant output low. Input coupling transistors
with up to eight emitter-base junctions and, therefore, eight-input NAND gates are constructed.
Storage time (the time it takes for the transistor to come out of saturation) is a major factor of propagation
delay for saturated BJT transistors. A long storage time limits switching speed of a standard TTL circuit.
Propagation delay can be decreased and the switching speed increased by placing a Schottky diode between the
base and collector of each transistor that might saturate. The resulting Schottky-clamped transistors then will
not go into saturation, effectively eliminating storage time, since the diode shunts current from the base into
the collector before the transistor can achieve saturation. Digital circuit designs implemented with TTL logic
almost exclusively use one of the Schottky subfamilies to take advantage of a significant improvement in
switching speed.

CMOS Logic Family

The vast majority of new circuit designs today utilize CMOS family devices. The active switching element in all
CMOS family circuits is the metal-oxide semiconductor field-effect transistor (MOSFET). CMOS stands for
complementary MOS transistors and refers to both types of MOSFET transistors, n-channel and p-channel,
used to design this type of switching circuit. While the physical construction and internal physics of a
MOSFET differ from the BJT, the circuit switching action of the two transistor types is quite similar. The
MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential
to the gate terminal as to the source. An n-channel MOSFET is turned on and has a very low channel
resistance when a high voltage with respect to the source is applied to the gate. A p-channel MOSFET operates
in the same fashion but with opposite polarities; the gate must be more negative than the source to turn on the
transistor.
A block diagram and schematic for a CMOS inverter circuit is shown in Figure 1.2. Note that the circuit has
a simpler and more compact design than that for the TTL inverter. That is a major reason why MOSFET
integrated circuits have a higher circuit density than BJT integrated circuits and is one advantage that
MOSFET ICs have over BJT ICs. As a result, CMOS is used in all levels of integration, from SSI through Very
Large Scale Integration (VLSI).
When a high logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned off and
the n-channel MOSFET Q2 will be turned on. This causes the output to be shorted to ground through the
low-resistance path of Q2’s channel. The turned-off Q1 has a very high channel resistance and acts almost like
an open channel.

# 2006 by Taylor & Francis Group, LLC

 VDD
+VDD

VG1 pull-up
(p-channel)
Q1 Q1

VD1
input output input output
VD2
VG2 pull-down Q2
(n-channel)
Q2

input Q1 VD1 Q2 VD2 output

hi off open on low low

low on hi off open hi

FIGURE 1.2 CMOS inverter circuit and operation.

VDD VDD

Q1 Q2
(p-chan) (p-chan)
X
X

A
Q3
A
(n-chan)

B
Q4
B
(n-chan)
inputs transistors output
A B Q1 Q2 Q3 Q4 X
low low on on off off hi
low hi on off off on hi
hi low off on on off hi
hi hi off off on on low

FIGURE 1.3 CMOS two-input NAND circuit and operation.

When a low logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned on and
the n-channel MOSFET Q2 will be turned off. This causes the output to be shorted to VDD through the low-
resistance path of Q1’s channel. The turned-off Q2 has a very high channel resistance and acts almost like an
open channel.
CMOS NAND gates are constructed by paralleling p-channel MOSFETs, one for each input, and putting in
series an n-channel MOSFET for each input, as shown in the block diagram and schematic of Figure 1.3.

# 2006 by Taylor & Francis Group, LLC

The NAND gate will produce a low output only when both Q3 and Q4 are turned on, creating a low-resistance
path from the output to ground through the two series channels. This can be achieved by having a high input on
both A and B. This input condition will also turn off Q1 and Q2. If either input A or input B or both are low, the
respective parallel MOSFET will be turned on, providing a low resistance path for the output to VDD. This will
also turn off at least one of the series MOSFETs, resulting in a high resistance path for the output to ground.

ECL Logic Family

ECL is the highest-speed logic family available. While it does not offer as large a variety of IC chips as are
available in the TTL or CMOS families, it has been popular for logic applications requiring high-speed
switching, although its power consumption is also relatively high. ECL power consumption, however, does not
increase as the switching frequency increases. At frequencies above 20 MHz, the dynamic power consumption
of CMOS gates will continue to increase and exceed the per-gate consumption of ECL devices. Newer ECL
family devices are available that can be switched at a rate faster than 3GHz.
The active switching element used in ECL family circuits is also the NPN BJT. But unlike the TTL family,
which switches the transistors into saturation while turning them on, ECL switching is designed to prevent
driving the transistors into saturation. Whenever bipolar transistors are driven into saturation, their switching
speed will be limited by the charge-carrier storage delay, a transistor operational characteristic. Thus, the
switching speed of ECL circuits will be significantly higher than that for TTL circuits. ECL operation is based
on switching a fixed amount of bias current, which is less than the saturation amount between two different
transistors. The basic circuit found in the ECL family is the differential amplifier. A bias circuit controls one
side of the differential amplifier, while the other is controlled by the logic inputs to the gate. This logic family is
also referred to as current-mode logic (CML), due to its current switching operation.

Logic Family Circuit Parameters

Digital circuits and systems operate in only two states, logic 1 and 0, usually represented by two different
voltage levels, a HIGH and a LOW. The two logic levels consist of a range of values with numerical quantities
dependent upon the specific family used. Minimum high-logic levels and maximum low-logic levels are
established by specifications for each family. Minimum device output levels for a logic high are called
VOH(min), and minimum input levels are called VIH(min). The abbreviations for maximum output and input

Volts Volts
Output Input
Output Input
5 Hi 5
VOHmin
VNH Hi
4 4
Hi
Hi VIHmin
3 3
VOHmin Disallowed
VNH Range Indeterminate
2 VIHmin 2 Range
Disallowed
Indeterminate
Range
Range
1 1 VILmax
VILmax VNL
VOLmax VNL
Lo
Lo Lo VOLmax
0 Lo 0
TTL family CMOS family (VDD = 5V)

FIGURE 1.4 TTL and CMOS family logic levels.

# 2006 by Taylor & Francis Group, LLC

 TABLE 1.3 Logic Signal Voltage Parameters for Selected Logic Subfamilies (in Volts)
Subfamily VOH(min) VOL(max) VIH(min) VIL(max)

74xx 2.4 0.4 2.0 0.8

74LSxx 2.7 0.5 2.0 0.8
74ASxx 2.5 0.5 2.0 0.8
74ALSxx 2.5 0.4 2.0 0.8
74Fxx 2.5 0.5 2.0 0.8
74HCxx 4.9 0.1 3.15 0.9
74HCTxx 4.9 0.1 2.0 0.8
74ACxx 3.8 0.4 3.15 1.35
74ACTxx 3.8 0.4 2.0 0.8
74AHCxx 4.5 0.1 3.85 1.65
74AHCTxx 3.65 0.1 2.0 0.8
10xxx 0.96 1.65 1.105 1.475
10Hxxx 0.98 1.63 1.13 1.48

low-logic levels are VOL(max) and VIL(max). Figure 1.4 shows the relationships between these parameters.
Logic voltage-level parameters for selected prominent logic subfamilies are illustrated in Table 1.3. As seen in
this illustration, there are many operational incompatibilities between major logic family types.
Noise margin is a quantitative measure of a device’s noise immunity. High-level noise margin (VNH) and
low-level noise margin (VNL) are defined in Equation (1.1) and Equation (1.2).

V NH ¼ V OHðminÞ  V IHðminÞ ð1:1Þ

V NL ¼ V ILðmaxÞ  V OLðmaxÞ ð1:2Þ

Using the logic voltage values in Table 1.3 for the selected subfamilies reveals that the highest noise immunity
is obtained with logic devices in the CMOS family while the lowest noise immunity is endemic to the ECL
family.
Switching circuit outputs are loaded by the inputs of the devices they are driving, as illustrated in Figure 1.5.
Worst-case input loading current levels and output driving current capabilities are listed in Table 1.4 for
various logic subfamilies. The fan-out of a driving device is the ratio between its output current capabilities at
each logic level and the corresponding gate-input current loading value.
Switching circuits based on bipolar transistors have fan-out that is limited primarily by the current-sinking
and current-sourcing capabilities of the driving device.
CMOS switching circuits are limited by the charging and discharging times associated with the output
resistance of the driving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on
switching frequency. With fewer capacitive loading inputs to drive, the maximum switching frequency of
CMOS devices will increase.
The switching speed of logic devices depends on the device’s propagation delay time. The propagation
delay of a logic device limits the frequency at which it can be operated. There are two propagation delay times
specified for logic gates: tPHL, delay time for the output to change from high to low, and tPLH, delay time for
the output to change from low to high. Average typical propagation delay times for a single gate are listed in
Table 1.5 for several logic subfamilies. The ECL family has the fastest switching speed.
The amount of power required by an IC is normally specified in terms of the amount of current ICC (TTL
family), IDD (CMOS family) or IEE (ECL family) drawn from the power supply. For complex IC devices, the
required supply current is given under specified test conditions. For TTL chips containing simple gates, the
average power dissipation PD(ave) is normally calculated from two measurements, ICCH (when all gate outputs
are high) and ICCL (when all gate outputs are low). Table 1.5 compares the static power dissipation of several
logic subfamilies. The ECL family has the highest power dissipation for switching frequencies below about

# 2006 by Taylor & Francis Group, LLC

 IIH1
Vsupply
current
sourcing
IOH(total)
IIH2
driving VOH
gate driven
gates
IIH3

Vsupply

IIL1

Vsupply

driving IOL(total)
gate IIL2
VOL Vsupply

current driven
sinking gates
IIL3

FIGURE 1.5 Current loading of driving gates.

TABLE 1.4 Worst Case Current Parameters for Selected Logic Subfamilies
Subfamily IOH(max) IOL(max) IIH(max) IIL(max)

74xx 400 mA 16 mA 40 mA 1.6 mA

74LSxx 400 mA 8 mA 20 mA 400 mA
74ASxx 2 mA 20 mA 20 mA 0.5 mA
74ALSxx 400 mA 8 mA 20 mA 100 mA
74Fxx 1 mA 20 mA 20 mA 0.6 mA
74HCxx 4 mA 4 mA 1 mA 1 mA
74HCTxx 4 mA 4 mA 1 mA 1 mA
74ACxx 24 mA 24 mA 1 mA 1 mA
74ACTxx 24 mA 24 mA 1 mA 1 mA
74AHCxx 8 mA 8 mA 1 mA 1 mA
74AHCTxx 8 mA 8 mA 1 mA 1 mA
10xxx 50 mA 50 mA 265 mA 0.5 mA
10Hxxx 50 mA 50 mA 265 mA 0.5 mA

20 MHz, while the lowest dissipation is found in the CMOS family. Power dissipation for the CMOS family is
directly proportional to gate-input signal frequency. For example, typically, the power dissipation for a CMOS
logic circuit will increase by a factor of 100 if input signal frequency is increased from 1 kHz to 100 kHz.
It is desirable to implement high speed (and, therefore, low propagation delay time) switching devices that
consume low amounts of power. Because of the nature of transistor switching circuits, it is difficult to attain

# 2006 by Taylor & Francis Group, LLC

 TABLE 1.5 Speed-Power Comparison for a Single Gate in
Selected Logic Subfamilies
Subfamily Propagation Delay Static Power Dissipation,
Time, ns (ave.) mW (per gate)

74xx 10 10
74LSxx 9.5 2
74Asxx 1.5 8.5
74ALSxx 4 1.2
74Fxx 3 6
74HCxx 8 0.003
74HCTxx 14 0.003
74Acxx 5 0.010
74ACTxx 5 0.010
74AHCxx 5.5 0.003
74AHCTxx 5 0.003
10xxx 2 25
10Hxxx 1 25

relationship between
input/output parameters

VOHmin > VIHmin

driving driven
circuit circuit
IOHmax > IIH

output input
parameters parameters

driving VOLmax < VILmax driven

circuit circuit
IOLmax > IIL

FIGURE 1.6 Circuit interfacing requirements.

high-speed switching with low power dissipation. The continued development of new IC logic families and
subfamilies is due largely to the trade-offs between these two device-switching parameters.

Interfacing between Logic Families

The interconnection of logic chips requires that input and output specifications be satisfied. Figure 1.6
illustrates voltage and current requirements. The driving chip’s VOHmin must be greater than the driven
circuit’s VIHmin, and the driver’s VOLmax must be less than VILmax for the loading circuit. Voltage level shifters
must be used to interface the circuits if these voltage requirements are not met. Of course, a driving circuit’s
output must not exceed the maximum- and minimum-allowable input voltages for the driven circuit. The
current sinking and sourcing ability of the driver circuit’s output must be greater than the total current
requirements for the loading circuit. Buffer gates or stages must be used if current requirements are not
satisfied. All chips within a single logic family are designed to be compatible with other chips in that family.
Mixing chips from multiple subfamilies together within a single digital circuit can have adverse effects on the
overall circuit’s switching speed and noise immunity.

# 2006 by Taylor & Francis Group, LLC

Defining Terms
Fan-out: The specification used to identify the limit to the number of loading inputs that can be reliably
driven by a driving device’s output.
Logic Level: The high or low value of a voltage variable, assigned as a 1 or a 0 state.
Noise Immunity: A logic device’s ability to tolerate input voltage fluctuation caused by noise without
changing its output state.
Propagation Delay Time: The time delay from when the input logic level to a device is changed until that
device produces the resultant output change.
Truth Table: A listing of the relationship of a circuit’s output produced for various combinations of logic
levels at the inputs.

References
N.P. Cook, Practical Digital Electronics, Upper Saddle River, NJ: Pearson Prentice-Hall, 2004.
R.K. Dueck, Digital Design with CPLD Applications and VHDL, 2nd ed., Albany, NY: Delmar Thomson
Learning, 2005.
T.L. Floyd, Digital Fundamentals, 8th ed., Upper Saddle River, NJ: Pearson Prentice-Hall, 2003.
D.D. Givone, Digital Principles and Design, New York, NY: McGraw-Hill, 2003.
W. Kleitz, Digital Electronics: A Practical Approach, 7th ed., Upper Saddle River, NJ: Pearson Prentice-Hall,
2005.
M.M. Mano, Digital Design, 3rd ed., Upper Saddle River, NJ: Pearson Prentice-Hall, 2002.
R.J. Tocci, N.S. Widmer, and G.L. Moss, Digital Systems: Principles and Applications, 9th ed., Upper Saddle
River, NJ: Pearson Prentice-Hall, 2004.
J.F. Wakerly, Digital Design: Principles and Practices, 3rd ed., Upper Saddle River, NJ: Pearson Prentice-Hall,
2001.

Further Information
Journals & Trade Magazines:
EDN, Highlands Ranch, CO: Reed Business Information.
Electronic Design, Cleveland, OH: Penton Media.
Electronic Engineering Times, Manhasset, NY: CMP Publications.
Internet Addresses for Digital Device Data Sheets:
Texas Instruments, Inc.: ,http://focus.ti.com/general/docs/scproducts.jsp..
ON Semiconductor: ,http://www.onsemi.com/site/products/taxonomy/..

1.2 Logic Gates (IC)1

Peter Graham
This section introduces and analyzes the electronic circuit realizations of the basic gates of the three technol-
ogies: transistor-transistor logic (TTL), emitter-coupled logic (ECL), and complementary metal-oxide semi-
conductor (CMOS) logic. These circuits are commercially available on small-scale integration chips and are
also the building blocks for more elaborate logic systems. The three technologies are compared with regard
to speed, power consumption, and noise immunity, and parameters are defined which facilitate these
comparisons. Also included are recommendations which are useful in choosing and using these technologies.

1
Based on P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-
Interscience, 1986, pp. 864–876. With permission.

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Gate Specification Parameters
Theoretically almost any logic device or system could be constructed by wiring together the appropriate
configuration of the basic gates of the selected technology. In practice, however, the gates are interconnected
during the fabrication process to produce a desired system on a single chip. The circuit complexity of a given
chip is described by one of the following four rather broad classifications:
. Small-Scale Integration (SSI). The inputs and outputs of every gate are available for external connection
at the chip pins (with the exception that exclusive OR and AND-OR gates are considered SSI).
. Medium-Scale Integration (MSI). Several gates are interconnected to perform somewhat more
elaborate logic functions such as flip-flops, counters, multiplexers, etc.
. Large-Scale Integration (LSI). Several of the more elaborate circuits associated with MSI are
interconnected within the integrated circuit to form a logic system on a single chip. Chips such as
calculators, digital clocks, and small microprocessors are examples of LSI.
. Very-Large-Scale Integration (VLSI). This designation is usually reserved for chips having a very high
density, 1000 or more gates per chip. These include the large single-chip memories, gate arrays, and
microcomputers.
Specifications of logic speed require definitions of switching times. These definitions can be found in the
introductory pages of most data manuals. Four of them pertain directly to gate circuits. These are (see also
Figure 1.7):
. LOW-to-HIGH Propagation Delay Time (tPLH). The time between specified reference points on the
input and output voltage waveforms when the output is changing from low to high.
. HIGH-to-LOW Propagation Delay Tune (tPHL). The time between specified reference points on the
input and output voltage waveforms when the output is changing from high to low.
. Propagation Delay Time (tPD). The average of the two propagation delay times: tPD ¼ (tPD þ tPHL)/2.
. LOW-to-HIGH Transition Time (tTLH). The rise time between specified reference points on the LOW-
to-HIGH shift of the output waveform.

FIGURE 1.7 Definitions of switching times. (Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical
Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, p. 865. With permission.)

# 2006 by Taylor & Francis Group, LLC

 . HIGH-to-LOW Transition Time (tTHL). The fall time between specified reference points on the HIGH-
to-LOW shift of the output waveform. The reference points usually are 10 and 90% of the voltage level
difference in each case.
Power consumption, driving capability, and effective loading of gates are defined in terms of currents.
. Supply Current, Outputs High (IxxH). The current delivered to the chip by the power supply when all
outputs are open and at the logical 1 level. The xx subscript depends on the technology.
. Supply Current, Outputs Low (IxxL). The current delivered to the chip by the supply when all outputs
are open and at the logical 0 level.
. Supply Current, Worst Case (Ixx). When the output level is unspecified, the input conditions are
assumed to correspond to maximum supply current.
. Input HIGH Current (IIH). The current flowing into an input when the specified HIGH voltage is applied.
. Input LOW Current (IIL). The current flowing into an input when the specified LOW voltage is applied.
. Output HIGH Current (IOH). The current flowing into the output when it is in the HIGH state. IOHmax
is the largest IOH for which VOH $ VOHmin is guaranteed.
. Output LOW Current (IOL). The current flowing into the output when it is in the LOW state. IOLmax
is the largest IOL for which VOL $ VOLmax is guaranteed.
The most important voltage definitions are concerned with establishing ranges on the logical 1 (HIGH) and
logical 0 (LOW) voltage levels.
. Minimum High-Level Input Voltage (VIHmin). The least positive value of input voltage guaranteed to
result in the output voltage level specified for a logical 1 input.
. Maximum Low-Level Input Voltage (VILmax). The most positive value of input voltage guaranteed to
result in the output voltage level specified for a logical 0 input.
. Minimum High-Level Output Voltage (VOHmin). The guaranteed least positive output voltage when
the input is properly driven to produce a logical 1 at the output.
. Maximum Low-Level Output Voltage (VOLmax). The guaranteed most positive output voltage when
the input is properly driven to produce a logical 0 at the output.
. Noise Margins. NMH ¼ VOHmin  VIHmin is how much larger the guaranteed least positive output
logical 1 level is than the least positive input level that will be interpreted as a logical 1. It represents
how large a negative-going glitch on an input 1 can be before it affects the output of the driven device.
Similarly, NML ¼ VILmax  VOLmax is the amplitude of the largest positive-going glitch on an input
0 that will not affect the output of the driven device.
Finally, three important definitions are associated with specifying the load that can be driven by a gate. Since
in most cases the load on a gate output will be the sum of inputs of other gates, the first definition
characterizes the relative current requirements of gate inputs.
. Load Factor (LF). Each logic family has a reference gate, each of whose inputs is defined to be a unit load in
both the HIGH and the LOW conditions. The respective ratios of the input currents IIH and IIL of a given input
to the corresponding IIH and IIL of the reference gate define the HIGH and LOW load factors of that input.
. Drive Factor (DF). A device output has drive factors for both the HIGH and the LOW
output conditions. These factors are defined as the respective ratios of IOHmax and IOLmax of the gate
to IOHmax and IOLmax of the reference gate.
. Fan-Out. For a given gate the fan-out is defined as the maximum number of inputs of the same type of
gate that can be properly driven by that gate output. When gates of different load and drive factors are
interconnected, fan-out must be adjusted accordingly.

Bipolar Transistor Gates

A logic circuit using bipolar junction transistors (BJTs) can be classified either as saturated or as nonsaturated
logic. A saturated logic circuit contains at least one BJT that is saturated in one of the stable modes of the circuit.

# 2006 by Taylor & Francis Group, LLC

In nonsaturated logic circuits none of the transistors is allowed to saturate. Since bringing a BJTout of saturation
requires a few additional nanoseconds (called the storage time), nonsaturated logic is faster. The fastest circuits
available at this time are emitter-coupled logic (ECL), with transistor-transistor logic (TTL) having Schottky
diodes connected to prevent the transistors from saturating (Schottky TTL) being a fairly close second. Both of
these families are nonsaturated logic. All TTL families other than Schottky are saturated logic.

Transistor-Transistor Logic
TTL evolved from resistor-transistor logic (RTL) through the intermediate step of diode-transistor logic
(DTL). All three families are catalogued in data books published in 1968, but of the three only TTL is still
available.
The basic circuit of the standard TTL family is typified by the two-input NAND gate shown in Figure 1.8(a).
To estimate the operating levels of voltage and current in this circuit, assume that any transistor in saturation
has VCE ¼ 0.2 and VBE ¼ 0.75 V. Let drops across conducting diodes also be 0.75 V and transistor current
gains (when nonsaturated) be about 50. As a starting point, let the voltage levels at both inputs A and B be
high enough that T1 operates in the reversed mode. In this case the emitter currents of T1 are negligible, and

FIGURE 1.8 Two-input transistor-transistor logic (TTL) NAND gate type 7400: (a) circuit, (b) symbol, (c) voltage
transfer characteristic (Vi to both inputs), (d) truth table. (Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics
and Electrical Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, p. 867. With permission.)

# 2006 by Taylor & Francis Group, LLC

the current into the base of T1 goes out the collector to become the base current of T2. This current is readily
calculated by observing that the base of T1 is at 3 · 0.75 ¼ 2.25 V so there is a 2.75-V drop across the 4-kO
resistor. Thus IBI ¼ IB2 ¼ 0.7 mA, and it follows that T2 is saturated. With T2 saturated, the base of T3 is at
VC þ VBE4 ¼ 0.95 V. If T4 is also saturated, the emitter of T3 will be at VD3 þ VCE4 ¼ 0.95 V, and T3 will be
cut off. The voltage across the 1.6-kO resistor is 5  0.95 ¼ 4.05 V, so the collector current of T2 is about
2.5 mA. This means the emitter current of T2 is 3.2 mA. Of this, 0.75 mA goes through the 1-kO resistor,
leaving 2.45 mA as the base current of T4. Since the current gain of T4 is about 50, it will be well into
saturation for any collector current less than 100 mA, and the output at C is a logic 0. The corresponding
minimum voltage levels required at the inputs are estimated from VBE4 þ VECI, or about 1.7 V.
Now let either or both of the inputs be dropped to 0.2 V. T1 is then biased to saturation in the normal mode,
so the collector current of T1 extracts the charge from the base region of T2. With T2 cut off, the base of T4 is at
0 V and T4 is cut off. T3 will be biased by the current through the 1.6-kO resistor (R3) to a degree regulated
by the current demand at the output C. The drop across R3 is quite small for light loads, so the output level
at C will be VCC  VBE3  VD3, which will be about 3.5 V corresponding to the logical 1.
The operation is summarized in the truth table in Figure 1.8(d), identifying the circuit as a two-input
NAND gate. The derivation of the input-output voltage transfer characteristic [Figure 1.8(c)], where Vi is
applied to inputs A and B simultaneously, can be found in most digital circuit textbooks. The sloping portion
of the characteristic between Vi ¼ 0.55 and 1.2 V corresponds to T2 passing through the active region in going
from cutoff to saturation.
Diodes D1 and D2 are present to damp out ‘‘ringing’’ that can occur, for example, when fast voltage level
shifts are propagated down an appreciable length (20 cm or more) of microstripline formed by printed circuit
board interconnections. Negative overshoots are clamped to the 0.7 V across the diode.
The series combination of the 130-O resistor, T3, D3, and T4 in the circuit of Figure 1.8(a), forming what is
called the totem-pole output circuit, provides a low impedance drive in both the source (output C ¼ 1) and
sink (output C ¼ 0) modes and contributes significantly to the relatively high speed of TTL. The available
source and sink currents, which are well above the normal requirements for steady state, come into play during
the charging and discharging of capacitive loads. Ideally T3 should have a very large current gain and the
130-O resistor should be reduced to 0. The latter, however, would cause a short-circuit load current which
would overheat T3, since T3 would be unable to saturate. All TTL families other than the standard shown in
Figure 1.8(a) use some form of Darlington connection for T3, providing increased current gain and
eliminating the need for diode D3. The drop across D3 is replaced by the base emitter voltage of the added
transistor T5. This connection appears in Figure 1.9(a), an example of the 74Hxx series of TTL gates that
increases speed at the expense of increased power consumption, and in Figure 1.9(b), a gate from the 74Lxx
series that sacrifices speed to lower power dissipation.
A number of TTL logic function implementations are available with open collector outputs. For example,
the 7403 two-input NAND gate shown in Figure 1.10 is the open collector version of Figure 1.8(a). The open
collector output has some useful applications. The current in an external load connected between the open
collector and VCC can be switched on and off in response to the input combinations. This load, for example,
might be a relay, an indicator light, or an LED display. Also, two or more open collector gates can share a
common load, resulting in the anding together of the individual gate functions. This is called a ‘‘wired-AND
connection.’’ In any application, there must be some form of load or the device will not function. There is a
lower limit to the resistance of this load which is determined by the current rating of the open collector
transistor. For wired-AND applications the resistance range depends on how many outputs are being wired
and on the load being driven by the wired outputs. Formulas are given in the data books. Since the open
collector configuration does not have the speed enhancement associated with an active pull-up, the low to high
propagation delay (tPLH) is about double that of the totem-pole output. It should be observed that totem-pole
outputs should not be wired, since excessive currents in the active pull-up circuit could result.

Nonsaturated TTL. Two TTL families, the Schottky (74Sxx) and the low-power Schottky (74LSxx), can
be classified as nonsaturating logic. The transistors in these circuits are kept out of saturation by the
connection of Schottky diodes, with the anode to the base and the cathode to the collector.

# 2006 by Taylor & Francis Group, LLC

FIGURE 1.9 Modified transistor-transistor logic (TTL) two-input NAND states: (a) type 74Hxx, (b) type 74L00. (Source:
P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-
Interscience, 1986, p. 868. With permission.)

FIGURE 1.10 Open collector two-input NAND gate. (Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and
Electrical Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, p. 868. With permission.)

Schottky diodes are formed from junctions of metal and an n-type semiconductor, the metal fulfilling the
role of the p-region. Since there are thus no minority carriers in the region of the forward-biased junction,
the storage time required to bring a pn junction out of saturation is eliminated. The forward-biased drop
across a Schottky diode is around 0.3 V. This clamps the collector at 0.3 V less than the base, thus maintaining
VCE above the 0.3-V saturation threshold. Circuits for the two-input NAND gates 74LS00 and 74S00 are given
in Figure 1.11(a) and (b). The special transistor symbol is a short-form notation indicating the presence of the
Schottky diode, as illustrated in Figure 1.11(c).

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FIGURE 1.11 Transistor-transistor logic (TTL) nonsaturated logic. (a) Type 74LS00 two-input NAND gate, (b) type 74S00
two-input NAND gate, (c) significance of the Schottky transistor symbol. (Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern
Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, p. 870. With permission.)

Note that both of these circuits have an active pull-down transistor T6 replacing the pull-down resistance
connected to the emitter of T2 in Figure 1.9. The addition of T6 decreases the turn-on and turn-off times of T4.
In addition, the transfer characteristic for these devices is improved by the squaring off of the sloping region
between Vi ¼ 0.55 and 1.2 V [see Figure 1.8(c)]. This happens because T2 cannot become active until T6 turns
on, which requires at least 1.2 V at the input.

# 2006 by Taylor & Francis Group, LLC

TABLE 1.6 Comparison of TTL Two-Input NAND Gates
Propagation Noise
Supply Current Delay Time Margins

TTL ICCHa ICCL tPLH tPHL NMH NML Load Drive Fan-
Type (mA) (mA) (ns) (ns) (V) (V) Factor, H/L Factor, H/L Out

74F00 2.8 10.2 2.9 2.6 0.7 0.3 0.5/0.375 25/12.5 33

74S00 10 20 3 3 0.7 0.3 1.25/1.25 25/12.5 10
74H00 10 26 5.9 6.2 0.4 0.4 1.25/1.25 12.5/12.5 10
74LS00 0.8 2.4 9 10 0.7 0.3 0.5/0.25 10/5 20
7400 4 12 11 7 0.4 0.4 1/1 20/10 10
74L00 0.44 1.16 31 31 0.4 0.5 0.24/0.1125 5/2.25 20
a
See text for explanation of abbreviations.
Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-
Interscience, 1986, p. 871. With permission.

The diode AND circuit of the 74LS00 in place of the multi-emitter transistor will permit maximum input
levels substantially higher than the 5.5-V limit set for all other TTL families. Input leakage currents for 74LSxx
are specified at Vi ¼ 10 V, and input voltage levels up to 15 V are allowed. The 74LSxx has the additional
feature of the Schottky diode D1 in series with the 100-O output resistor. This allows the output to be pulled
up to 10 V without causing a reverse breakdown of T5. The relative characteristics of the several versions of the
TTL two-input NAND gate are compared in Table 1.6. The 74F00 represents one of the new technologies that
have introduced improved Schottky TTL in recent years.
TTL Design Considerations. Before undertaking construction of a logic system, the wise designer
consults the information and recommendations provided in the data books of most manufacturers. Some of
the more significant tips are provided here for easy reference.
1. Power supply, decoupling, and grounding. The power supply voltage should be 5 V with less than 5%
ripple factor and better than 5% regulation. When packages on the same printed circuit board are
supplied by a bus there should be a 0.05-mF decoupling capacitor between the bus and the ground for
every five to ten packages. If a ground bus is used, it should be as wide as possible, and should surround
all the packages on the board. Whenever possible, use a ground plane. If a long ground bus is used, both
ends must be tied to the common system ground point.
2. Unused gates and inputs. If a gate on a package is not used, its inputs should be tied either high or low,
whichever results in the least supply current. For example, the 7400 draws three times the current with
the output low as with the output high, so the inputs of an unused 7400 gate should be grounded.
An unused input of a gate, however, must be connected so as not to affect the function of the active
inputs. For a 7400 NAND gate, such an input must either be tied high or paralleled with a used input.
It must be recognized that paralleled inputs count as two when determining the fan-out. Inputs that are
tied high can be connected either to VCC through a 1-kO or more resistance (for protection from supply
voltage surges) or to the output of an unused gate whose input will establish a permanent output high.
Several inputs can share a common protective resistance. Unused inputs of low-power Schottky TTL
can be tied directly to VCC, since 74LSxx inputs tolerate up to 15 V without breakdown. If inputs of
low-power Schottky are connected in parallel and driven as a single input, the switching speed is
decreased, in contrast to the situation with other TTL families.
3. Interconnection. Use of line lengths of up to 10 in. (5 in. for 74S) requires no particular precautions,
except that in some critical situations lines cannot run side by side for an appreciable distance without
causing cross talk due to capacitive coupling between them. For transmission line connections, a gate
should drive only one line, and a line should be terminated in only one gate input. If overshoots are a
problem, a 25- to 50-O resistor should be used in series with the driving gate input and the receiving
gate input should be pulled up to 5 V through a 1-kO resistor. Driving and receiving gates should

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 have their own decoupling capacitors between the VCC and ground pins. Parallel lines should have
a grounded line separating them to avoid cross talk.
4. Mixing TTL subfamilies. Even synchronous sequential systems often have asynchronous features such
as reset, preset, load, and so on. Mixing high-speed 74S TTL with lower speed TTL (74LS for example)
in some applications can cause timing problems resulting in anomalous behavior. Such mixing is to be
avoided, with rare exceptions which must be carefully analyzed.
Emitter-Coupled Logic
ECL is a nonsaturated logic family where saturation is avoided by operating the transistors in the common
collector configuration. This feature, in combination with a smaller difference between the HIGH and LOW
voltage levels (less than 1 V) than other logic families, makes ECL the fastest logic available at this time. The
circuit diagram of a widely used version of the basic two-input ECL gate is given in Figure 1.12. The power
supply terminals VCC1, VCC2, VEE, and VTT are available for flexibility in biasing. In normal operation, VCC1
and VCC2 are connected to a common ground, VEE is biased to 5.2 V, and VTT is biased to 2 V. With these
values the nominal voltage for the logical 0 and 1 are, respectively, 1.75 and 0.9 V. Operation with the VCC
terminals grounded maximizes the immunity from noise interference.
A brief description of the operation of the circuit will verify that none of the transistors saturates. For the
following discussion, VCC1 and VCC2 are grounded, VEE is 5.2 V, and VTT is 2 V. Diode drops and base-
emitter voltages of active transistors are 0.8 V.
First, observe that the resistor-diode (D1 and D2) voltage divider establishes a reference voltage of 0.55 V at
the base of T3, which translates to 1.35 V at the base of T2. When either or both of the inputs A and B are at
the logical 1 level of 0.9 V, the emitters of T1A, T1B, and T2 will be 0.8 V lower, at 1.7 V. This establishes the
base-emitter voltage of T2 at 1.35(1.7) ¼ 0.35 V, so T2 is cut off. With T2 off, T4 is biased into the active
region, and its emitter will be at about 0.9 V, corresponding to a logical 1 at the (A þ B) output. Most of
the current through the 365-O emitter resistor, which is [1.7(5.2)]/0.365 ¼ 9.6 mA, flows through the
100-O collector resistor, dropping the base voltage of T5 to 0.96 V. Thus the voltage level at the output
terminal designated (A þ B) is 1.76 V, corresponding to a logical 0.
When both A and B inputs are at the LOW level of 1.75 V, T2 will be active, with its emitter voltage at
1.350.8 ¼  2.15 V. The current through the 365-O resistor becomes [2.15(5.2)]/0.365 ¼ 8.2 mA.

FIGURE 1.12 Emitter-coupled logic basic gate (ECL 10102): (a) circuit, (b) symbol. (Source: P. Graham, ‘‘Gates,’’ in
Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-Interscience, 1986, p. 872. With
permission.)

# 2006 by Taylor & Francis Group, LLC

This current flows through the 112-O resistor pulling the base of T4 down to 0.94 V, so that the (A þ B)
output will be at the LOW level of 1.75 V. With T1A and T1B cut off, the base of T5 is close to 0.0 V, and the
(A þ B) output will therefore be at the nominal HIGH level of 0.9 V.
Observe that the output transistors T4 and T5 are always active and function as emitter followers, providing
the low-output impedances required for driving capacitive loads. As T1A and/or T1B turn on, and T2 turns off
as a consequence, the transition is accomplished with very little current change in the 365-O emitter resistor.
It follows that the supply current from VEE does not undergo the sudden increases and decreases prevalent in
TTL, thus eliminating the need for decoupling capacitors. This is a major reason why ECL can be operated
successfully with the low noise margins which are inherent in logic having a relatively small voltage difference
between the HIGH and LOW voltage levels (see Table 1.7). The small level shifts between LOW and HIGH also
permit low propagation times without excessively fast rise and fall times. This reduces the effects of residual
capacitive coupling between gates, thereby lessening the required noise margin. For this reason the faster ECL
(100xxx) should not be used where the speed of the 10xxx series is sufficient. A comparison of three ECL series
is given in Table 1.7. The propagation times tPLH and tPHL and transition times tTLH and tTHL are defined in
Figure 1.7. Transitions are between the 20 and 80% levels.
The 50-O pull-down resistors shown in Figure 1.12 are connected externally. The outputs of several gates can
therefore share a common pull-down resistor to form a wired-OR connection. The open emitter outputs also
provide flexibility for driving transmission lines, the use of which in most cases is mandatory for interconnecting
this high-speed logic. A twisted pair interconnection can be driven using the complementary outputs (A þ B)
and (A þ B) as a differential output. Such a line should be terminated in an ECL line receiver (10114).
Since ECL is used in high-speed applications, special techniques must be applied in the layout and inter-
connection of chips on circuit boards. Users should consult design handbooks published by the suppliers
before undertaking the construction of an ECL logic system.
While ECL is not compatible with any other logic family, interfacing buffers, called translators, are available.
In particular, the 10124 converts TTL output levels to ECL complementary levels, and the 10125 converts
either single-ended or differential ECL outputs to TTL levels. Among other applications of these translators,
they allow the use of ECL for the highest speed requirements of a system while the rest of the system uses the
more rugged TTL. Another translator is the 10177, which converts the ECL output levels to n-channel
metal-oxide semiconductor (NMOS) levels. This is designed for interfacing ECL with n-channel memory
systems.

TABLE 1.7 Comparison of ECL Quad Two-Input NOR Gates (VTT ¼ VEE ¼ 5.2 V, VCC1 ¼ 0 V)
Power Supply Power Supply Propagation Transition Noise
Terminal Current Delay Time Time Margins

ECL VEE IE tPLHa tPHL tTLHb tTHLb NMH NML Test

Type (V) (mA) (ns) (ns) (ns) (ns) (V) (V) Load

ECL II
1012 5.2 18c 5 4.5 4 6 0.175 0.175 Fan-out of 3
95102 5.2 11 2 2 2 2 0.14 0.145 50 O
10102 5.2 20 2 2 2.2 2.2 0.135 0.175 50 O
ECL III
1662 5.2 56c 1 1.1 1.4 1.2 0.125 0.125 50 O
100102d 4.5 55 0.75 0.75 0.7 0.7 0.14 0.145 50 O
11001e 5.2 24 0.7 0.7 0.7 0.7 0.145 0.175 50 O
a
See text for explanation of abbreviations.
b
20 to 80% levels.
c
Maximum value (all other typical).
d
Quint 2-input NOR/OR gate.
e
Dual 5/4-input NOR/OR gate.
Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. Belove, Ed., New York: Wiley-
Interscience, 1986, p. 873. With permission.

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Complementary Metal-Oxide Semiconductor (CMOS) Logic
Metal-oxide semiconductor (MOS) technology is prevalent in LSI systems due to the high circuit densities
possible with these devices. p-Channel MOS was used in the first LSI systems, and it still is the cheapest to
produce because of the higher yields achieved due to the longer experience with PMOS technology. PMOS,
however, is largely being replaced by NMOS (n-channel MOS), which has the advantages of being faster (since
electrons have greater mobility than holes) and having TTL compatibility. In addition, NMOS has a higher
function/chip area density than PMOS, the highest density in fact of any of the current technologies. Use of
NMOS and PMOS, however, is limited to LSI and VLSI fabrications. The only MOS logic available as SSI and
MSI is CMOS (complementary MOS).
CMOS is faster than NMOS and PMOS, and it uses less power per function than any other logic. While it is
suitable for LSI, it is more expensive and requires somewhat more chip area than NMOS or PMOS. In many
respects it is unsurpassed for SSI and MSI applications. Standard CMOS (the 4000 series) is as fast as low-
power TTL (74Lxx) and has the largest noise margin of any logic type.
A unique advantage of CMOS is that for all input combinations the steady-state current from VDD to
VSS is almost zero because at least one of the series FETs is open. Since CMOS circuits of any complexity
are interconnections of the basic gates, the quiescent currents for these circuits are extremely small, an
obvious advantage which becomes a necessity for the practicality of digital watches, for example, and one
which alleviates heat dissipation problems in high-density chips. Also a noteworthy feature of CMOS
digital circuits is the absence of components other than FETs. This attribute, which is shared by PMOS
and NMOS, accounts for the much higher function/chip area density than is possible with TTL or ECL.
During the time the output of a CMOS gate is switching there will be current flow from VDD to VSS,
partly due to the charging of junction capacitances and partly because the path between VDD and VSS
closes momentarily as the FETs turn on and off. This causes the dc supply current to increase in
proportion to the switching frequency in a CMOS circuit. Manufacturers specify that the supply voltage
for standard CMOS can range over 3 V # VDD  VSS # 18 V, but switching speeds are slower at the
lower voltages, mainly due to the increased resistances of the ‘‘on’’ transistors. The output switches
between low and high when the input is midway between VDD and VSS, and the output logical 1 level will
be VDD and the logical 0 level VSS [Figure 1.13(c)]. If CMOS is operated with VDD ¼ 5 V and VSS ¼ 0 V,
the VDD and VSS levels will be almost compatible with TTL except that the TTL totem-pole output high
of 3.4 V is marginal as a logical 1 for CMOS. To alleviate this, when CMOS is driven with TTL a 3.3-kO

FIGURE 1.13 (a) Complementary metal-oxide semiconductor (CMOS) NAND gate, (b) NOR gate, and (c) inverter
transfer characteristic. (Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. Belove,
Ed., New York: Wiley-Interscience, 1986, p. 874. With permission.)

# 2006 by Taylor & Francis Group, LLC

pull-up resistor between the TTL output and the
common VCC, VDD supply terminal should be
used. This raises VOH of the TTL output to 5 V.
All CMOS inputs are diode protected to prevent
static charge from accumulating on the FET gates and
causing punch-through of the oxide insulating layer.
A typical configuration is illustrated in Figure 1.14.
Diodes D1 and D2 clamp the transistor gates between
VDD and VSS. Care must be taken to avoid input
voltages that would cause excessive diode currents. For
this reason manufacturers specify an input voltage
constraint from VSS  0.5 V to VDD þ 0.5 V. FIGURE 1.14 Diode protecion of input transistor gates.
The resistance Rs helps protect the diodes from 200 O , Rs , k O. (Source: P. Graham, ‘‘Gates,’’ in Handbook
excessive currents but is introduced at the expense of Modern Electronics and Electrical Engineering, C. Belove,
of switching speed, which is deteriorated by the Ed., New York: Wiley-Interscience, 1986, p. 875. With
permission.)
time constant of this resistance and the junction
capacitances.
Advanced versions of CMOS have been developed which are faster than standard CMOS. The first of these
to appear were designated 74HCxx and 74HCTxx. The supply voltage range for this series is limited to 2 V #
VDD  VSS # 6 V. The pin numbering of a given chip is the same as its correspondingly numbered TTL
device. Furthermore, gates with the HCT code have skewed transfer characteristics which match those of its
TTL cousin, so that these chips can be directly interchanged with low-power Schottky TTL.
More recently, a much faster CMOS has appeared and carries the designations 74ACxx and 74ACTxx. These
operate in the same supply voltage range and bear the same relationship with TTL as the HCMOS. The driving
capabilities (characterized by IOH and IOL) of this series are much greater, such that they can be fanned out to
10 low-power Schottky inputs.
The three types of CMOS are compared in Table 1.8. The relative speeds of these technologies are best
illustrated by including in the table the maximum clock frequencies for D flip-flops. In each case, the
frequency given is the maximum for which the device is guaranteed to work. It is worth noting that a typical
maximum clocking of 160 MHz is claimed for the 74ACT374 D flip-flop.

TABLE 1.8 Comparison of Standard, High-Speed, and Advanced High-Speed CMOS

Standard CMOS High-Speed Advanced
NORGates CMOS Inverter CMOS Inverter

Parameter Symbol Unit 4001B 4011UB 74HC04 74HCT04 74AC04 74ACT04

Supply voltage VDD-VSS V 15 15 6 5.5 5.5 5.5

Input voltage thresholds VIHmin V 11 12.5 4.2 2 3.85 2
VILmax V 4 2.5 1.8 0.8 1.65 0.8
Guaranteed output VOHmin V 13.5 13.5 5.9 4.5 4.86 4.76
levels at maximum IO VOLmax V 1.5 1.5 0.1 0.26 0.32 0.37
Maximum output currents IOH mA 8.8 3.5 4 4 24 24
IOL mA 8.8 8.8 4 4 24 24
Noise margins NML V 2.5 2.5 1.7 0.54 1.33 0.43
NMH V 2.5 2.5 1.7 2.5 1.01 1.24
Propagation times tPLH ns 40 40 16 15 4 4.3
tPHL ns 40 40 16 17 3.5 3.9
Max input current leakage IINmax mA 0.1 0.1 0.1 0.1 0.1 0.1
D-flip-flop max frequency 4013 B 74HC3 74 74HCT374 A 74AC37 4 74ACT37 4
(guaranteed minimum) fmax MHz 7.0 N.A. 35 30 100 100

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CMOS Design Considerations
Design and handling recommendations for CMOS, which are included in several of the data books, should be
consulted by the designer using this technology. A few selected recommendations are included here to
illustrate the importance of such information.
1. All unused CMOS inputs should be tied either to VDD or VSS, whichever is appropriate for proper
operation of the gate. This rule applies even to inputs of unused gates, not only to protect the inputs
from possible static charge buildup, but to avoid unnecessary supply current drain. Floating gate inputs
will cause all the FETs to be conducting, wasting power and heating the chip unnecessarily.
2. CMOS inputs should never be driven when the supply voltage VDD is off, since damage to the input-
protecting diodes could result. Inputs wired to edge connectors should be shunted by resistors to VDD
or VSS to guard against this possibility.
3. Slowly changing inputs should be conditioned using Schmitt trigger buffers to avoid oscillations that
can arise when a gate input voltage is in the transition region.
4. Wired-AND configurations cannot be used with CMOS gates, since wiring an output HIGH to an
output LOW would place two series FETs in the ‘‘on’’ condition directly across the chip supply.
5. Capacitive loads greater than 5000 pF across CMOS gate outputs act as short circuits and can overheat
the output FETs at higher frequencies.
6. Designs should be used that avoid the possibility of having low impedances (such as generator outputs)
connected to CMOS inputs prior to power-up of the CMOS chip. The resulting current surge when
VDD is turned on can damage the input diodes.
While this list of recommendations is incomplete, it should alert the CMOS designer to the value of the
information supplied by the manufacturers.

Choosing a Logic Family

A logic designer planning a system using SSI and MSI chips will find that an extensive variety of circuits is
available in all three technologies: TTL, ECL, and CMOS. The choice of which technology will dominate the
system is governed by what are often conflicting needs, namely, speed, power consumption, noise immunity,
cost, availability, and the ease of interfacing. Sometimes the decision is easy. If the need for a low static power
drain is paramount, CMOS is the only choice. It used to be the case that speed would dictate the selection;
ECL was high speed, TTL was moderate, and CMOS low. With the advent of advanced TTL and, especially,
advanced CMOS the choice is no longer clear-cut. All three will work at 100 MHz or more. ECL might be used
since it generates the least noise because the transitions are small, yet for that same reason it is more
susceptible to externally generated noise. Perhaps TTL might be the best compromise between noise
generation and susceptibility. Advanced CMOS is the noisiest because of its rapid rise and fall times, but the
designer might opt to cope with the noise problems to take advantage of the low standby power requirements.
A good rule is to use devices which are no faster than the application requires and which consume the least
power consistent with the needed driving capability. The information published in the manufacturers’ data
books and designer handbooks is very helpful when choice is in doubt.

Defining Term
Logic gate: Basic building block for logic systems that controls the flow of pulses.

References
Advanced CMOS Logic Designers Handbook, Dallas: Texas Instruments, Inc., 1987.
C. Belove and D. Schilling, Electronic Circuits, Discrete and Integrated, 2nd ed., New York: McGraw-Hill, 1979.
FACT Data, Phoenix: Motorola Semiconductor Products, Inc., 1989.
Fairchild Advanced Schottky TTL, California: Fairchild Camera and Instrument Corporation, 1980.

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W.I. Fletcher, An Engineering Approach to Digital Design, Englewood Cliffs, N.J.: Prentice-Hall, 1980.
High Speed CMOS Logic Data, Phoenix: Motorola Semiconductor Products, Inc., 1989.
P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., New York: Cambridge University Press, 1990.
MECL System Design Handbook, Phoenix: Motorola Semiconductor Products, Inc., 1988.
H. Taub and D. Schilling, Digital Integrated Electronics, New York: McGraw-Hill, 1977.
The TTL Data Book for Design Engineers, Dallas: Texas Instruments, Inc., 1990.

Further Information
An excellent presentation of the practical design of logic systems using SSI and MSI devices is developed in the
referenced book An Engineering Approach to Digital Design by William I. Fletcher. The author pays particular
attention to the importance of device speed and timing.
The Art of Electronics by Horowitz and Hill is particularly helpful for its practical approach to interfacing
digital with analog.
Everything one needs to know about digital devices and their interconnection can be found somewhere in
the data manuals, design handbooks, and application notes published by the device manufacturers.
Unfortunately, no single publication has it all, so the serious user should acquire as large a collection of these
sources as possible.

1.3 Bistable Devices

Richard S. Sandige and Lynne A. Slivovsky
This section explores bistable devices, also commonly referred to as bistables, latches or flip-flops. Bistable
devices are memory elements and can store one bit of information, such as a logic 1 or a logic 0 state. Latches
and flip-flops are used to implement finite-state machines, counters and registers and are part of the
configurable logic in complex programmable-logic devices and field programmable-gate arrays. Distinguishing
behavior between a latch and a flip-flop is when the output changes due to a change in one or more inputs.
A latch is considered transparent when changes in inputs, and hence stored data, immediately appear at the
output. Edge-triggered flip-flops that change state with respect to a clock signal are not transparent. Output
changes are triggered by a clock event.
The simplest bistable device consists of a pair of cross-coupled inverters where the output from one inverter
feeds the input of the other, as depicted in Figure 1.15. After this circuit is powered up the value stored in the
device, or the Q state, becomes indeterminate and will randomly fall into one of three states shown in
Figure 1.15(b). Logic 0 or logic 1, corresponding to a low- or high-output voltage at Q, are stable states. Once
the circuit moves to one of these states, it will never leave it. There is one metastable point in the center of the
graph that would also satisfy the device’s physical properties. But the likelihood of the circuit spending
significant time in the metastable state is low, since any noise applied to the circuit would cause it to change to
one of the stable states.

Latches
Replacing the inverters in the bistable element in Figure 1.15 with NOR gates provides the inputs to the
bistable that can cause a change in state. Figure 1.16 shows an example of a basic set-reset (S-R) NOR latch
implementation using two cross-coupled NOR gates. The logic symbol recommended for the S-R NOR latch
by the Institute of Electrical and Electronics Engineers (IEEE) is shown to the right of the logic circuit
implementation.
The S-R latch consists of a set (S) input, a reset (R) input and two outputs (Q and QN) that are normally
complements of each other. Table 1.9 shows the operation of the S-R circuit. For S R ¼ 00, Q ¼ last Q,
illustrating that the output for the next state Q is the same as for the present state output. For S R ¼ 01,
Q ¼ 0, specifying that the output for the next state is reset. For S R ¼ 10, Q ¼ 1, indicating that the output

# 2006 by Taylor & Francis Group, LLC

 Stable
Vout1=Vin2

Vin1 Vout1
Q

Metastable

Vin2 Vout2
QN
Stable

Vin1=Vout2
(a) (b)

FIGURE 1.15 (a) The bistable element is composed of two inverter gates. (b) This shows the relationship between the
input and output inverter voltages of the bistable element. The circuit has two stable operating points and one metastable
operating point, all satisfying the circuit’s transfer functions.

R Q

S Q

R Q

S QN

FIGURE 1.16 Set-Reset (S-R). This latch is constructed using NOR gates, in a configuration similar to the bistable
element and its corresponding circuit symbol.

for the next state is set. In most cases, the input conditions S R ¼ 11 are not allowed for two reasons. If S
R ¼ 11, then the QN output for the bistable element is not logically correct, as it is for all other input
combinations. The second reason is more subtle since the next state of the bistable can be set or reset due to a
critical race condition when the inputs are changed from 11 to 00. Such unpredictability is not desirable and
therefore, the S R ¼ 11 condition is generally not allowed. Latches and flip-flops that contain both a Q and a
QN output (complementary outputs) provide double-rail outputs.
The S-R NAND latch in Figure 1.17 uses two cross-coupled NAND gates. In most cases, the input
conditions S R ¼ 00 (S R ¼ 11) are not allowed, for the same reasons provided above for the S-R NOR latch.
For S R ¼ 01 (S R ¼ 10), Q ¼ 1 indicating that the output for the next state is set. For S R ¼ 10 (S R ¼ 01),
Q ¼ 0 specifying that the output for the next state is reset. For S R ¼ 11 (S R ¼ 00), Q ¼ last illustrating that
the output for the next state Q is the same as for the present stateoutput.
A gated, S-R latch is generated by AND-ing the inputs S and R with input C, as depicted in Figure 1.18. The
C input acts to enable the latch. When C is asserted, the S-R latch behaves as described. When C is negated,
both data inputs are logic 0, and the latch maintains its current state. Whatever value the output has when
C goes to 0 is latched, captured or stored (memory mode).
The D latch in Figure 1.19 avoids the SR ¼ 11 input conditions by guaranteeing that the data inputs are
complements of each other. The S and R inputs are reduced to a single input, named D for data. The schematic
symbol and characteristic table for the gated D latch circuit are shown in Figure 1.20. When input C is

# 2006 by Taylor & Francis Group, LLC

 TABLE 1.9 Operation of the S-R Latch
S R Q QN

0 0 last Q last QN
0 1 0 1
1 0 1 0
1 1 0 0

S Q

S Q

R Q
QN
R

FIGURE 1.17 Basic S-R NAND latch and corresponding circuit symbol.

R
Q

S Q

C C

R Q
QN
S

FIGURE 1.18 Gated S-R latch, where input C behaves like an enable signal.

D
Q

QN

FIGURE 1.19 Gated D latch circuit based on the S-R NOR latch.

# 2006 by Taylor & Francis Group, LLC

asserted, the D latch is transparent and the value of data input D appears at output Q. When input C is
negated, the last value of data input D is stored in the latch. The D latch is level-sensitive with respect to C.
The next section discusses devices that are edge-sensitive.

Flip-Flops
Early types of flip-flops were master-slave, pulse-triggered devices that had no data-lockout circuitry and
caused a storage error if improperly used due to 1s and 0s catching. To prevent 1s and 0s catching, data-
lockout (also called variable-skew) circuitry was added to some master-slave flip-flop types. Due to the
improved design features and popularity of edge-triggered flip-flops, master-slave flip-flops are not
recommended for newer designs and, in some cases, have been made obsolete by manufacturers, making them
difficult to obtain even for repair parts. For this reason, only edge-triggered flip-flops will be discussed.
Four types of edge-triggered flip-flops are presented here. These are the D, J-K, T and S-R flip-flops. The
D type is the most commonly used because its circuitry generally takes up less space on an IC chip and because
most engineers consider it an easier device to use as the excitation equation to drive the D input is identical to
the next state equation. An example of a positive, edge-triggered D flip-flop circuit is shown in Figure 1.21.

(a) (b)
C D Q QN
D Q 0 0 last Q last QN
0 1 last Q last QN
1 0 0 1
C Q
1 1 1 0

FIGURE 1.20 Gated D latch: (a) schematic symbol and (b) characteristic table.

PRE

LATCH 1
CLR Q

LATCH 3

Q
CLK

LATCH 2

FIGURE 1.21 Positive, edge-triggered, D flip-flop circuit. (Source: Modified from R.S. Sandige, Modern Digital Design,
New York: McGraw-Hill, 1990, p. 490.)

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 TABLE 1.10 Characteristic Table of a Positive
Edge-Triggered, D Flip-Flop
D CLK Q QN

0 " 0 1
1 " 1 0
x 0 last Q last QN
x 1 last Q last QN

D D Q D Q Q

C C QN
Q Q

CLK

FIGURE 1.22 Positive edge-triggered D flip-flop circuit constructed from two D latches.

CLR
J

CLK

K
PRE

FIGURE 1.23 Negative, edge-triggered, J-K flip-flop circuit. (Source: Modified from R.S. Sandige, Modern Digital Design,
New York: McGraw-Hill, 1990, p. 493.)

The characteristic table illustrating the operation of this flip-flop is shown in Table 1.10. At the rising edge of
the clock input, the value at D is stored in the flip-flop. The D flip-flop can also be constructed by using two
D latches, as shown in Figure 1.22.
The main difference between a latch and an edge-triggered flip-flop is their transparency. The gated D latch
is transparent (the Q output follows the D input when the control input C ¼ l) and it latches, captures or
stores the value at the D input when the control input C shifts to 0. The positive edge-triggered D flip-flop is
never transparent from the time of its data input D to that of its output Q. When the clock is 0, the output Q
does not follow the D input and remains unchanged; however, the value at the D input is latched, captured or
stored when the clock makes a transition from 0 to 1. The flip-flop changes state only on the rising edge of the
clock. Edge-triggered flip-flops are desirable for feedback applications due to their lack of transparency.
Their outputs can be fed back as inputs to the device without causing oscillation. This is true for all types of
edge-triggered flip-flops. A negative, edge-triggered, J-K flip-flop circuit is shown in the circuit diagram in
Figure 1.23 with its corresponding IEEE symbol. Notice that the J-K flip-flop requires eight logic gates,

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 TABLE 1.11 Characteristic Table of a Positive, Edge-
Triggered, J-K Flip-Flop
J K Q

0 0 Iast Q (hold)
0 1 0 (clear)
1 0 1 (set)
1
1 1 Q ðtoggleÞ

D Q J Q Q S Q
T
CLK CLK
CLK Q K Q CLK Q R Q

Q+ = D Q+ = J·Q + KQ Q+ = T ⊕ KQ Q+ = S + R·Q

FIGURE 1.24 Common edge-triggered flip-flops and their characteristic equations.

compared to only six logic gates for the D flip-flop in Figure 1.21. The characteristic table for this negative,
edge-triggered flip-flop is shown in Table 1.11. When the J and K inputs are both 1 and the clock makes a 1 to
0 transition, the flip-flop toggles, and the next state output Q changes to the complement of the present state.
By connecting J and K together and renaming it T for toggle, one can obtain a negative, edge-triggered, T flip-
flop.
The behavior of each flip-flop in the characteristic tables can be captured in a characteristic equation. This
equation describes the behavior of a flip-flop at a clock edge. Figure 1.24 shows the D and J-K flip-flops with
their characteristic equations along with the T (or toggle) flip-flop and the S-R flip flop.
Since bistable devices are asynchronous, fundamental-mode, sequential logic circuits, only one input is
allowed to change at a time. This means that for proper operation for a basic latch, only one of the data inputs
S or R for an S-R NOR latch (and the NAND implementation) may be changed at one time. For proper
operation of a gated latch, the data inputs S and R or data input D must meet minimum setup and hold-time
requirements; i.e., the data input(s) must be stable for a minimum period before the control input C changes
the latch from the transparent mode to the memory mode. For proper operation of an edge-triggered flip-flop,
data inputs must meet minimum setup and hold time requirements relative to the clock changing from 0 to 1
(positive edge-triggered) or from 1 to 0 (negative edge-triggered).
An interesting exercise is to design a circuit for a D flip-flop using a J-K flip-flop and some additional gates.
In general, a circuit can be designed that implements the characteristic equation of any flip-flop by using any
other flip-flop and some added logic.

Defining Terms
Bistable, latch and flip-flop: Substitutions for the term bistable device.
Critical race: A change in two input variables resulting in an unpredictable output value for a bistable
device.
Edge-triggered: Term describing the edge of a positive or negative pulse applied to the control input of a
nontransparent bistable device to latch, capture or store the value indicated by the data input(s).
Fundamental mode: Operating mode of a circuit allowing only one input to change at a time.
Memory element: A bistable device or element providing data storage for a logic 1 or a logic 0 state.
Characteristic table: A tabular representation that illustrates the operation of various bistable devices.
Setup and hold time: The time required for the data input(s) to be held stable before or after the control
input C changes to latch, capture or store the value indicated by the data input(s).

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Toggle: Change in state from logic 0 to logic 1 or from logic 1 to logic 0 in a bistable device.
Transparent mode: Mode of a bistable device where the output responds to data-input signal changes.
Volatile device: A memory or storage device that loses its storage capability when power is removed.

References
ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions, New York, NY: Institute of
Electrical and Electronics Engineers.
ANSI/IEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams, New York, NY: Institute of Electrical and
Electronics Engineers.
R.S. Sandige, Digital Design Essentials, Upper Saddle River, NJ: Prentice Hall, 2002.
Texas Instruments, The TTL Data Book, Advanced Low-Power Schottky, Advanced Schottky, vol. 3, Dallas,
TX: Texas Instruments, 1984.
J.F. Wakerly, Digital Design Principles and Practices, 3rd ed., Upper Saddle River, NJ: Prentice Hall, 2001
(Updated).

Further Information
Journals published by the IEEE contain the latest information on a variety of topics related to computer design
and realization, including digital devices, logic and circuit design. Look in IEEE Transactions on Computers,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and IEEE Transactions on Very Large-Scale
Integration Systems.

1.4 Optical Devices

H.S. Hinton
Since the first demonstration of optical logic devices in the late 1970s, there have been many different
experimental devices reported. Figure 1.25 categorizes optical logic devices into four main classes. The first
division is between all-optical and optoelectronic devices. All-optical devices are devices that do not use
electrical currents to create the nonlinearity required by digital devices. These devices can be either single-pass
devices (light passes through the nonlinear material once) or they can use a resonant cavity to further enhance
the optical nonlinearity (multiple passes through the same nonlinear material). Optoelectronic devices, on the
other hand, use electrical currents and electronic devices to process a signal that has gone through an optical-
to-electrical conversion process. The output of these devices is either provided by electrically driving an optical
source such as a laser or LED (detect/emit) or by modulating some external light source (detect/modulate).
Below each of these categories are listed some of the devices that have been experimentally demonstrated.

All-Optical Devices
To create an all-optical logic device requires a medium that will allow one beam of light to affect another. This
phenomenon can arise from the cubic response to the applied field. These third-order processes can lead to
purely dielectric phenomena, such as irradiance-dependent refractive indices. By exploiting purely dielectric
third-order nonlinearities, such as the optical Kerr effect, changes can be induced in the optical constants of
the medium which can be read out directly at the same wavelength as that inducing them. This then opens up
the possibilities for digital optical circuitry based on cascadable all-optical logic gates. Although there have
been many different all-optical gates demonstrated, this section will only briefly review the soliton gate (single-
pass) and one example of the nonlinear Fabry–Perot structures (cavity-based).

# 2006 by Taylor & Francis Group, LLC

 FIGURE 1.25 Classification of optical logic devices.

FIGURE 1.26 Soliton NOR gate: (a) physical implementation, (b) timing diagram.

Single-Pass Devices
An example of an all-optical single-pass optical logic gate is the soliton NOR gate. It is an all-fiber logic gate
based on time shifts resulting from soliton dragging. A NOR gate consists of two birefringent fibers connected
through a polarizing beamsplitter with the output filtered by a polarizer as shown in Figure 1.26. The clock
pulse, which provides both gain and logic level restoration, propagates along one principal axis in both fibers.
For the NOR gate the fiber length is trimmed so that in the absence of any signal the entering clock pulse will
arrive within the output time window corresponding to a ‘‘1.’’ When either or both of the input signals are
incident, they interact with the clock pulse through soliton dragging and shift the clock pulse out of the
allowed output time window creating a ‘‘0’’ output. In soliton dragging two temporally coincident, ortho-
gonally polarized pulses interact in the fiber through cross-phase modulation and shift each other’s velocities.
This velocity shift converts into a time shift after propagating some distance in the fiber. To implement the
device, the two input signal pulses g1 and g2 are polarized orthogonal to the clock. The signals are timed so
that g1 and the clock pulse coincide at the input to the first fiber and g2 and the clock pulse coincide (in the
absence of g1) at the input to the second fiber. At the output the two input signals are blocked by the polarizer,

# 2006 by Taylor & Francis Group, LLC

allowing only the temporally modified clock pulse to
pass. In a prototyped demonstration this all-optical
NOR gate required 5.8 pJ of signal energy and provided
an effective gain of 6.

Cavity-Based Devices
Cavity-based optical logic devices are composed of two
highly reflective mirrors that are separated by a distance
d [Figure 1.27(a)]. The volume between the mirrors,
referred to as the cavity of the etalon, is filled with a
nonlinear material possessing an index of refraction
that varies with intensity according to nc ¼ n0 þ n2 gc
where n0 is the linear index of refraction, n2 is the
nonlinear index of refraction, and gc is the intensity of
light within the cavity. In the ideal case, the character-
istic response of the reflectivity of a Fabry–Perot cavity,
Rfp, is shown in Figure 1.27(b). At low intensities, the
cavity resonance peak is not coincident with the
wavelength of the incident light; thus the reflectivity is
high, which allows little of the incident light to be
transmitted [solid curves in Figure 1.27(b)]. As the
intensity of the incident light g increases, so does the
intercavity light intensity which shifts the resonance
peak [dotted curve in Figure 1.27(b)]. This shift in the
resonant peak increases the transmission which in turn
reduces the reflectivity. This reduction in c will continue
with increasing g until a minimum value is reached.
It should be noted that in practice all systems of
interest have both intensity-dependent absorption
and n2.
FIGURE 1.27 (a) Nonlinear Fabry–Perot etalon, (b)
To implement a two-input NOR gate using the
reflection peaks of NLFP, and (c) NLFP in reflection
characteristic curve shown in Figure 1.27(c) requires a (NOR).
third input which is referred to as the bias beam, gb. This
energy source biases the etalon at a point on its
operating curve such that any other input will
exceed the nonlinear portion of the curve moving the etalon from the high reflection state. This is illustrated
in Figure 1.27(c) where the gb combines with the inputs g1 and g2 to exceed the threshold of the nonlinear
characteristic curve.
The first etalon-based optical logic device was in the form of a non-linear interference filter (NLIF).
A simple interference filter has a general form similar to a Fabry–Perot etalon, being constructed by
depositing a series of thin layers of transparent material of various refractive indices on a transparent
substrate. The first several layers deposited form a stack of alternating high and low refractive indices, all of
optical thickness equal to one quarter of the operating wavelength. The next layer is a low integer (1–20)
number of half wavelengths thick and finally a further stack is deposited to form the filter. The two outer
stacks have the property of high reflectivity at one wavelength, thus playing the role of mirrors forming a
cavity. A high finesse cavity is usually formed when both mirrors are identical, i.e., of equal reflectivity.
However, unlike a Fabry–Perot etalon with a nonabsorptive material in the cavity, matched (equal) stack
reflectivities do not give the optimum cavity design to minimize switch power because of the absorption in
the spacer (which may be necessary to induce nonlinearity). A balanced design which takes into account the
effective decrease in back mirror reflectivity due to the double pass through the absorbing cavity is
preferable and also results in greater contrast between bistable states. The balanced design is easily achieved

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Exploring the Variety of Random
Documents with Different Content
pleased to accept of this as a token that you are not forgotten by,
my very dear friend,

Yours, &c. under ten thousand obligations, and in the best

bonds,

G. W.

LETTER MCCLXII.
To Mr. D――.

Bristol, April 29, 1762.

My very dear Mr. D――,

H OW have I been contriving to come over in one of the mast

ships lately sailed for New-England? But the hour is not yet
come. Hasten it, O glorious Emmanuel, for thy great name’s sake!
Surely a sea voyage would help to brace up this relaxed tabernacle.
Blessed be God, I am now enabled to preach four or five times a
week; but it is with much weakness. I long to hear how it is with you
in this Spanish war. Mr. Robinson I find was cast away, but hath
escaped with his life. Just now I have seen a letter to Mrs. P――e
from Mr. H――s, by which I find he is at Bethesda, and talks of
returning to England. I hope the Spanish war will prevent this last
motion, at least for some time. My love to him and all. Persevere in
praying me over. I have just now heard, that there is a packet for
me at London from Georgia. How could you draw on me for so large
a sum as an hundred and forty-seven pounds? Lord, help me!
Yesterday at Kingswood I saw the ship that is to bring this, ready to
sail. I hope I am not too late; and if any letters come from any of
you by this post (as I hear the Carolina ships are arrived), God
willing, they shall be answered by, my very dear Mr. D――,

Yours, &c. in our common Lord,

G. W.

LETTER MCCLXIII.
To Mrs. W――.

Bristol, May 4, 1762.

Dear Mrs. W――,

I THANK you heartily for your kind letter, and desire to bless the
Lord of all lords for the good news it contains. If the foot of pride
doth not come against those that speak for Jesus, all will be well. I
see it is always darkest before break of day. O that we could always
remember that blessed promise, “At evening-tide it shall be light.”
The archers have of late shot sorely at me and grieved me. Job’s
friends were his greatest trials, when God’s hand pressed his body
sore. So it hath been with me. But if we are brought out when tried
like gold, we shall only lose our dross. O that this may be my happy
case! Lord, I believe; help thou my unbelief! Blessed be his name for
a little revival in my bondage! For these three weeks past, I have
been enabled to preach four or five times. Not once without a
special blessing. Join with me in crying, Grace, grace! But my body
still continues weak. O blessed prospect of its being glorified by and
by! Come, Lord Jesus, come quickly! Continue to pray for me.
Remember me most heartily to all, as being, dear Mrs. W――,

Their and your most ready servant for Christ’s sake,

 G. W.

LETTER MCCLXIV.
To Mrs. C――.

Bristol, May 4, 1762.

Dear Mrs. C――,

Y OUR kind letter came to hand a few days ago. The convoy being
driven back, gives me an opportunity of returning you hearty
thanks. Mr. R――’s draught will lie hard upon me; but I will
endeavour to get it paid. I am glad A――w and G――r are put out.
It would have saved me pounds to have had it done long ago. As it
is war time, nobody can blame you for lessening the family to the
utmost. The intended change at Ephrata pleaseth me much. I see if
we will wait, Providence will open for us some way or another. O
that the door was open for my coming over! Perhaps it may be ere
the Summer is over. Grant it, O God, for Jesus Christ’s sake! I have
sometimes the hopes of being braced up again for a little future
service. With some difficulty I preach four or five times a week; but
you would scarce know me, I am so swoln with wind, and so
corpulent. Blessed be God for the prospect of a glorious resurrection!
For the present, adieu. I fear the ship will be gone. God bless you all.
Pray do you and Mr. D―― be particular in your accounts. Hearty
love to Mrs. P――l: God comfort her. You will shew this to Mr. D――.
I must add no more, but hearty love and ten thousand thanks from,
my dear friends,

Yours, &c. &c. in our glorious Head,

G. W.
 ♦LETTER MCCLXV.
To Mr. S―― S――.

Rodborough, May 21, 1762.

My very dear Friend,

T HOUGH I hope to be in London on Tuesday or Wednesday next,

yet I cannot come thither without troubling you with another
line. Blessed be God, it leaves me in better bodily health, than when
I wrote last. Through divine mercy, preaching four or five times a
week did not hurt me; and twice or thrice I have been enabled to
take the field: in my opinion, a greater honour than to be monarch
of the universe. London cares, and London labours, I expect, will
soon bring me low again. But as Messrs. D―― and K―― are
coming up, I hope soon to slip away and get strength, and then hunt
for precious souls again. How gladly would I bid adieu to cieled
houses, and vaulted roofs! Mounts are the best pulpits, and the
heavens the best sounding-boards. O for power equal to my will! I
would fly from pole to pole, publishing the everlasting gospel of the
Son of God. I know you would lend me the wings of prayer. Jesus in
answer give the wings of faith and love, and we shall then quickly
soar to thy bosom, where

Sin and strife and sorrow cease,

And all is calm and joy and peace.

I write this at a house built for dear Mr. A――s. From his window is a
prospect perhaps of thirty miles. I have wished you here with your
telescope. But if the footstool is so glorious, what must the throne
be? Come, Lord Jesus, come quickly! I am interrupted by company.
Good night, my very dear friend, good night! Most cordial respects
await dear Mrs. S―― and your daughter. Dear Mr. A――s is weak
like myself, but joins in sending due and hearty respects. We have
had most blessed seasons. Grace! grace! In heaven you will be
rewarded for all favours conferred on

Yours, &c. &c. in the best bonds,

G. W.

♦ “LETTRER” replaced with “LETTER”

LETTER MCCLXVI.
To Mrs. C――.

London, May 28, 1762.

Dear Mrs. C――.

I AM just now come to town for a few days, sensibly better by my

country excursion. Once more I have had the honour of taking
the field, and have now some hopes of not being as yet quite thrown
aside as a broken vessel. Help me to praise Him, whose mercy
endureth for ever. Why do you persist in keeping poor Mr. D―― in
suspense? If not done before, I expect to marry you both
immediately upon my arrival, but do not stay for that. Your hint
about Mr. S――’s being inclined to the ministry, made me smile. Mr.
R――’s account shall be paid as soon as possible. But I beg no such
thing may be done again. This is wrote in very great haste, hearing
that the ship is gone. I wrote to all from Bristol, very lately. This
must now do for all. God bless and reward you. Amen and Amen! I
am, dear Mrs. C――,

Yours, &c. &c. in Jesus,

G. W.

LETTER MCCLXVII.
To Mr. R―― K――n.

Norwich, July 31, 1762.

My very dear Friend,

T HOUGH you never mentioned a word concerning the letter I sent

you when at Bristol, yet this doth not discourage me from
dropping you a few lines, now I am put into Norwich-Dock, in order
to refit for another expedition. The Holland one last month, was, I
trust, profitable to myself and others; and if ever my usefulness is to
be continued at London, I must be prepared for it, by a longer
itineration both by land and water. At present, blessed be God, I can
preach once a day, and it would do your heart good to see what an
influence attends the word. All my old times are revived again. On
next Monday, God willing, I shall set forwards to Lincolnshire,
Yorkshire, &c. You that are in cieled houses, and under vaulted roofs
(which I do not grudge you) will not forget a poor pilgrim, who
desires no other pulpit but a mount, no other sounding board but
the heavens. I hope dear Mr. J―― is recovered of his indisposition,
and that your wife and his, with yourself, are increasing with all the
increase of God. My cordial respects and most hearty love attend
you, and all that are so kind as to enquire after a worthless worm.
As I shall not write to-night, be pleased to inform my wife that you
heard of my welfare, and in so doing, you will add to the obligations
already laid upon, my very dear Mr. K――n,

Yours, &c. in our Jesus,

G. W.

LETTER MCCLXVIII.
To the Reverend Mr. T――.

Edinburgh, September 2, 1762.

I AM just this moment returned from Glasgow, where I have been

enabled to preach every day, and twice at Cambuslang.
Auditories were large, and Jesus smiled upon my feeble labours. God
willing, I shall leave this place on Wednesday next; but I despair of
seeing you. I have heard nothing of Mr. M――n and V――n since I
left them at Leeds. What a mercy, that we are sure of meeting in
heaven! Surely, you will not go before me thither. Must it be always
juniores priores? Adieu. Cordial respects await your whole self. Lord
Jesus be with your spirits! I fear the carrier will be gone. Accept
these few rusty filings from, my very dear friend,

Yours, &c. &c. &c. in our glorious Jesus,

G. W.

September 9.

Thus far I went on Friday; but found that was the wrong day to
send. Since then, I have been helped to preach every day. The Kirk
hath been a Bethel. Grace! grace! On Monday, God willing, I shall set
off. Follow with your prayers.
 Yours, &c. &c.

G. W.

LETTER MCCLXIX.
To Mr. D――.

Sunderland, September 19, 1762.

My dear Mr. D――,

I CAN only send you a few lines: but I hope they will be acceptable
ones. Your last packet came to my hands yesterday. Blessed be
God that all is so well! You will be glad to hear, that I can preach
once a day, and that I have now a prospect of embarking soon. We
expect peace, and I hope the places in London will be provided for.
Pray keep the family as small as you can. Sickness lowers my
circumstances. But Jesus is all in all. I hope to see dear Mr. S――k’s
friends in a few days. I am glad he is at Ephrata. Tender love to him
and his, to dear Mrs. C――, Mrs. P――l, and to all. I can no more. I
write this at a venture, to send by way of Scotland, where the
Redeemer hath been owning my feeble labours. Grace! grace! When
I come to London, God willing, you shall hear again from, my very
dear friends,

Yours, &c. &c. in our common Lord,

G. W.

LETTER MCCLXX.
 To Mr. R―― K――n.

Leeds, September 25, 1762.

Dear Sir,

W HAT a pity that I cannot answer your kind letter, by telling you
where to meet me! but it is impracticable. I am just now
setting forwards towards London, but fear I cannot reach it before
Sunday. My chaise wanted repairing here. O how good hath Jesus
been to a worthless worm! Once a day preaching, I can bear well;
more hurts me. What shall I do with the chapel and tabernacle? Lord
Jesus, be thou my guide and helper! He will! he will. Send word to
tabernacle that you heard from me. We have had sweet seasons.
Grace! grace! To his never-failing mercy do I commend your whole
dear self, and all that are so kind as to enquire after, my very dear
friend,

Yours, &c. in our common Lord,

G. W.

LETTER MCCLXXI.
To Mrs. C――.

London, October 15, 1762.

Dear Mrs. C――,

I WISH to answer your last in person. I hope the time is now

drawing near. I count the weeks, and days, and hours. Lord
Jesus, direct my goings in thy way. Blessed be God that you live in
such harmony! A house thus united in Jesus, will stand. I shall bring
only one Mr. W――t, who takes care of me. I would not have Mr.
H――s to think of stirring till he sees me. This I write in great haste.
I am enabled to preach once a day. Give thanks! give thanks! and
continue to pray for, dear Mrs. C――,

Yours, &c. in our glorious Emmanuel,

G. W.

LETTER MCCLXXII.
To Mr. A―― K――.

Bristol, Numbers 29, 1762.

G OD willing, I shall set off for Plymouth to-morrow morning, and

hope to see you all on Thursday evening, or Friday. Let grand
preparations be made; as a candle, a book, and a table. Above all,
much prayer, that I may not again relapse at Plymouth; as Bristol
people do threaten me for coming at this time of the year. Blessed
be God, we have good seasons. I like Mr. B――n’s, better than a
boarding school for little maidens. A word to the wise is enough.
Adieu! The Lord be with you all. Cease not to pray for, my dear
Timothy,

Yours, &c. in our common Lord,

G. W.

LETTER MCCLXXIII.
 To Mr. S―― S――.

Plymouth, December 4, 1762.

H OW was I disappointed, two Mondays, of seeing and conversing

with my very dear Mr. S――! London, London, how dost thou
weigh this mortal body down! If it be no odds, I would visit my dear
friend again on a Wednesday. Perhaps on that day I may not be so
fatigued. I feel in preaching, what you do in business. However, I
must not complain. Once a day, I can manage quite well. Bristol was
a refreshing place indeed. Congregations were very large, and a
most gracious gale of divine influences attended the word preached.
Being under a positive promise to come here before I left England, I
embraced this opportunity. Through mercy, I preached last night,
and find no hurt this morning. Many young people, I hear, are under
great awakenings. May such hostilities never cease! O to begin to
begin to wage an eternal war with the devil, the world, and the
flesh. Still continue to help me, dear Sir, with your prayers. I would
fain die sword in hand. You will not blame me for this ambition. I
believe you are pretty much tinctured this way yourself. The Captain
of our salvation approves of it. That in all your spiritual battles, He
may be your shield and exceeding great reward, is the hearty prayer
of, my invaluable friend,

Yours, &c. &c. in the best bonds,

G. W.

LETTER MCCLXXIV.
To Mrs. Elizabeth W――d.

Plymouth, December 5, 1762.

Y OU did very wrong, in not letting me know of your mother’s
necessities. She was a widow indeed. But now she is above the
reach of every thing. O for patience to wait till we are sent for to
that place, where the weary are at rest! I am weary of the world, of
the church, and of myself. But Jesus will not leave us in the latter
stages of our road. Blessed be his name, we have had pleasant
seasons at Bristol, and two good gales here. I cannot get up to
London till near Christmas-day. As affairs are circumstanced, every
thing there tends to weigh me down. O that patience may have its
perfect work! Let me always know your wants. It is your own fault if
you lack any thing, whilst I have a farthing. You and your friend
must prepare a great entertainment; for I intend dining with you
when I come to town. Ere long we shall sit down and eat bread in
our heavenly Father’s kingdom. Come, Lord Jesus, come quickly! I
know who joins in saying, Amen! with, my dear old faithful friend
and servant,

Yours, &c. for Christ’s sake,

G. W.

LETTER MCCLXXV.
To Mr. R―― K――n.

Plymouth, December 5, 1762.

My dear steady Friend,

I MUST not be out of town, without sending my dear Mr. K――n a

few loving lines. Blessed be God for a few steady friends! they
are rarities even in the church of God. But the church is in a
wilderness; ere long it will be in Canaan. No briars or thorns there.
All glory be to Him who hath prepared such a rest for the purchase
of his blood. Amen. Hallelujah! You will be glad to hear, that both
here and at Bristol, souls are under real awakenings. Though I
preach in much weakness, an infinitely condescending Jesus
vouchsafes to come down in glorious gales of his blessed Spirit. This
is all in all. But these are only streams. Ere long we shall drink at the
fountain head. Do you not long to leap your seventy years? Blessed
be God, we are nearer and nearer. Fly, fly, O time! welcome,
welcome long wished for eternity! But I must not enlarge. We are
going to the Lord’s table. Adieu! Hearty love awaits your whole self.
In heaven I will thank you for all favours conferred upon, my dear
friend,

Yours in the Friend of sinners,

G. W.

LETTER MCCLXXVI.
To Mr. A―― K――.

Bristol, December 12, 1762.

T HROUGH divine mercy, we got here yesterday about three in the

afternoon, all well, excepting that I lost my watch in the way. If
it teacheth me to be more on my watch in the best things, it will be
rather a gain. Lord, help me in every thing to give thanks! I do not
repent my Plymouth journey. Thanks to all for their great
kindnesses. Thanks, eternal thanks to the God of all, for giving us his
presence! It is better than life. I have not yet seen your daughter,
but I hear she is well. Tell Sarah not to murder so dear a child.
Hugging to death is cruelty indeed. You will take the hint about my
little servitor. I charge you both, as you will answer it at the bar of
God, to teach them to be servant like, but not servile. Adieu! I must
away to sacrament. O for such a one as we had last Sunday! I felt, I
felt parting! O for the time when we shall part no more! Tender love
to Mr. S――, his mother, brother, Mr. D――, and all; your servants
not excepted. Sarah, adieu! Mind and get up in a morning to pray,
before you get into shop. I make no apology for this, because you
are a friend to, my dear man,

Yours, &c. in our common Lord,

G. W.

LETTER MCCLXXVII.
To Mr. R―― K――n.

Thursday evening. January 15, 1763.

My dear Friend,

D O meet me to-morrow by two o’clock, or rather one, at Mr.

B――n’s, at Cannonbury-house. I have something of
importance to communicate. Not to keep you in suspense, it is to
beseech you, jointly with Mr. H――y and Mr. B――n, as trustees, to
take upon you the whole care, both inward and outward, of the
affairs of Tottenham-court chapel and tabernacle, and all other my
concerns in England: this one thing being settled, I have nothing to
retard my visit to America, to which I think there is a manifest call at
this time, both as to the bracing up my poor feeble crazy body, and
adjusting all things relating to Bethesda. O that the Lord may incline
your heart to accept this trust! It will take off this ponderous load
that oppresses me much. Consider, dear Sir, it is for God! for whose
glory, I am convinced that you and my other dear friends have a
single eye and disinterested heart. O may he richly reward you for
this and all your labours of love! Fail not of meeting me at the time
and place above-mentioned. Mr. H――y and Mr. H―― D――s, God
willing, will be there. The Lord Jesus be with us all! My dear friend,

Yours, &c. &c. indeed and indeed, in Jesus,

G. W.

LETTER MCCLXXVIII.
To Mr. R―― K――n.

Leeds, March 6, 1763.

My very dear Friend,

Y OU have heard, I suppose, of my progress to, and employ at

Everton. Jesus was there. Last Thursday evening we came to
these parts, where I have preached twice, and been closely
employed in writing my little piece entitled, Observations, &c. in
answer to the Bishop of Gloucester. Perhaps a day or two more may
compleat it. Say nothing, but pray on. The next letters may be
directed to Edinburgh, under cover to ―― H――n, Esq.; Post-Master
general. You shall hear, God willing, when I have fixed upon a ship.
And I know you will pray that Jesus may be my convoy.

Only Thou our leader be,

And we still will follow Thee.

I could enlarge, but must away to my throne. Tell all at Tabernacle

and Chapel, where this leaves me. I send them and your whole self
most tender love, and ten thousand thanks; and beg you would add
to my obligations by praying for, my very dear friend,

Yours, &c. &c. in our common Lord,

G. W.

Postscript, To Mr. J――e.

My dear Sir,

A CCEPT a few lines from an old friend that loves you and yours
dearly. I would not be given to change, but, like my Master,
love to the end. His blessing be on you both! Accept thanks
unfeigned for all favours, and cease not to pray for, my very dear Mr.
J――,

Yours, &c. in Ours,

G. W.

LETTER MCCLXXIX.
To Mrs. M――.

Newcastle, March 13, 1763.

Dear Mrs. M――,

I T hath given me concern, since I left town, that through bodily

weakness, multiplicity of business, and pain of parting, I forgot
to answer your request about your deceased son. If not too late,
something like this may be inserted:
 “Near this place lies interred, William Middleditch, aged twelve
years, a desirable promising child; but an all-wise God thought
proper to remove him ――, 1762. His surviving parents desire to
subscribe to the divine will, and to say, The Lord gave, and the Lord
hath taken away: blessed be the name of the Lord.”

Ere long somebody will be writing an epitaph for our tombs. Change
of place doth not change my sentiments. “Come, Lord Jesus, come
quickly,” is the constant language of my heart. This leaves me thus
far advanced towards Scotland, where just such a ship as I want
awaits me. How good is Jesus! Fain would I sing,

Lord, obediently I go,

Gladly leaving all below.

I am sorry to find by the papers that Mr. B―― is taken up. To take
no notice would be the best method. A prison or outward
punishment is but a poor cure for enthusiasm, or a disordered
understanding. It may increase but not extinguish such an ignis
fatuus. Lord Jesus, give us all a right judgment in all things! Farewell.
Brethren, pray for us. We have had pleasant seasons at Everton,
Leeds, Aberford, Kippax, and here. Tender love to all that are so kind
as to enquire after a worthless worm. That you may be so supplied
as not to miss me one moment, is the earnest prayer of, dear Mrs.
M――,

Your sincere friend and ready servant in our common Lord,

G. W.

LETTER MCCLXXX.
 To Mr. S――.

Newcastle, March 13, 1763.

My very dear Friend,

I CANNOT go further, without dropping you a few lines. They leave

me thus far advanced in my journey to Scotland. My friends
write me word, that the ship Jenny, Captain Orr, a very discreet
person, sails from Greenock to Boston the middle of April. You will
pray, that the God of the sea and dry land will give me a safe, and, if
agreeable to his will, a speedy passage. On the road we have been
favoured with some sweet seasons. I have preached at Everton,
Leeds, Kippax, Aberford, and this place. Next sabbath I hope to be
at Edinburgh. On my way, I was enabled to finish a little thing in
answer to the present Bishop of Gloucester. If my friends think
proper to print it, you will find a parting testimony left behind me for
the good old Puritans and free-grace Dissenters, whom he sadly
maligns. Bless it, glorious Emmanuel, and it shall be blessed! Follow
me, follow me, my very dear Sir, with your constant prayers. Mine
will always be ascending for you and yours. Indeed I owe you much
love! You have often strengthened my hands in the Lord. Fain would
I sing,

Lord, obediently I go,

Gladly leaving all below;

Only Thou my leader be,

And I still will follow Thee.

And now, my dear friend, farewell. Ere long we shall meet in a better
climate, where
 Pain and sin and sorrow cease,

And all is calm and joy and peace.

Most cordial respects await dear Mrs. S―― and your daughter, if
continued in this dying world. Expect to hear, from time to time,
from, my very dear Sir,

Yours, &c. &c.

G. W.

LETTER MCCLXXXI.
To Mrs. W――.

Edinburgh, March 19, 1763.

Dear Mrs. W――,

I WAS quite concerned to see you so ill as I passed by you. I

charge you to want for nothing. Speak to Messrs. K――n or
H――y: they will supply you at any time. Do not be afraid to go to
the Tabernacle house. I will own and stand by my dear steady and
faithful servants and helpers. Such a one you have been. O for
heaven! There are no thorns and briars amongst God’s people there.
May our present ones fit us more and more for that place where

Sin and strife and sorrow cease,

And all is calm and joy and peace.

Follow me with your prayers. Tender love to all the conference. I
have no doubt of the Lord’s being with them. God be with you all
evermore! We have had good seasons at Everton, Leeds, Newcastle,
&c. in the way. Grace! grace! In about a month I expect to sail. A
good stock of prayers in that time, may be laid up for, dear Betty,
my old faithful friend and servant,

Yours, &c. &c. in Jesus,

G. W.

LETTER MCCLXXXII.
To the Reverend Mr. T――.

Edinburgh, March 26, 1763.

My dear Friend,

W HY not see each other once more? Perhaps, after my return

from Glasgow, I may be here a fortnight. My poor tabernacle
is so far restored, as to mount the gospel throne once a day.
Perhaps the sea air may brace me up a little more: but after all, it is
only like the glimmering of a candle before it goes out. Death will
light it up in a better world. Work on, my dear son, work on. The
night cometh when no man can work. O that I had done more for
the blessed Jesus! O that I could think more of what he hath done
for me! Never mind being counted singular. O that you may be more
and more vile every day! Happy they that are safe landed!

――――And happy, happy we,

Who soon their company shall see!

It is but for a little indeed. Come, Lord Jesus, come quickly! I know
you will heartily say, Amen. Cordial respects await Mrs. T――. The
Edinburgh prescriptions were the most blessed to me. My spirits are
much brisker than when here last. Grace! grace! O to lie low! Adieu,
my dear friend.

Yours, &c. &c. &c. in our common Lord,

G. W.

LETTER MCCLXXXIII.
To Mr. R―― K――n.

Edinburgh, March 26, 1763.

My dear Mr. K――n,

I THANK you for your kind letter, and thank the Lord ♦ of all lords
that matters go on so well. I am more than easy. The Redeemer
hath directed my choice, and will bless, assist, and reward those
employed. Ten thousand thanks to you all. You may act as you
please with respect to Mr. ――. His attending the Tabernacle when I
was well, and leaving it ever since I have been sick, doth not look
well at all: but please yourselves and you will please me. Do not
consult me in any thing, unless absolutely necessary. The Lord, I
trust and believe, will give you a right judgment in all things. But O
follow me with your prayers. On Monday I am going to see about
the ship. Now we have peace abroad, Lord Jesus give us peace at
home! I am sorry my little piece, entituled Observations, &c. is not
come out yet. Tender love to all. My dear old friend,

Yours, &c. &c. in Jesus,

 G. W.

♦ removed duplicate “of”

LETTER MCCLXXXIV.
To Mr. W――y.

Edinburgh, April 8, 1763.

Dear Mr. W――y,

I THANK you for your kind remembrance in Mr. W――’s. Indeed I

do not forget you. O that you may be a steady follower of Him,
who was not ashamed of being called the carpenter’s son! My prayer
to him is, that you may be daily more and more built up in his most
holy faith. But the way to heaven is a narrow way. No elbow room
for our lusts. What a blessing this! Lord Jesus, make us willing to be
made whole! Adieu. Tender love to all enquiring friends. I trust their
prayers are heard. The Redeemer vouchsafes to smile upon the
feeble labours of, my dear Mr. W――y,

Yours, &c. in Him,

G. W.

LETTER MCCLXXXV.
To Mr. K――n.
 Leith, May 14, 1763.

My dear old steady Friend,

W HY so fearful of writing a longer letter? The longer the better.

Blessed be God, though disappointed in embarking, by reason
of sickness, I can read, and write, and hope (notwithstanding a little
cold, which threw me somewhat back this week) soon to get upon
my throne again. The news about the congregations, you may well
guess rejoiced my poor heart. Surely Mr. H―― will not get to
heaven before me too. What an age do we live in! Children thus to
take the lead of their parents. Heavenly Father, not my will, but thine
be done! I expect to-morrow’s interview. A single eye will carry us
through all. A catholic spirit is the plague of bigots. Lord Jesus, cure
them of their bad distemper! I rejoice to hear that good Lady H――n
is so supported. Pray remember me in the kindest manner to dear
Mr. H――y. As I have not heard from him for two or three posts, I
fear he is worse. Pray let him know of my sending this; and inform
him of my having been able to go upon the water to-day for several
hours, and by land afterwards. Others can die, but I cannot. Father,
thy will be done! What a God do I serve? Physicians, friends on every
side of me. And what is all in all, the great physician comforting my
soul. Thank, O thank him in behalf of a worthless worm. Tender love
to Mrs. K――n, Mr. and Mrs. B――n, Mr. and Mrs. J――, and all dear
friends, who are so kind as to be concerned for me. You will be very
fine when all is painted. Blessed be God, I approve your conduct,
and love your spirit. Lord Jesus, make us all glorious within! I must
drop a line to dear Mr. A―― about Mr. H――, or you should have
more from, my dear old steady friend,

Yours, &c. &c. &c. in Jesus,

G. W.
 LETTER MCCLXXXVI.
To the Reverend Mr. T――.

Greenock, June 4, 1763.

My dear Friend,

A THOUSAND thanks for your kind letters. Jesus is kind. I am

better, and just going on board the Fanny, bound to Rapanach,
in Virginia. Yours to good Lady H――n is taken care of. I hear her
daughter died well, and that her Ladyship is comforted and resigned.
Blessed be God! Adieu. Follow me with your prayers, as being

Ever yours, &c.

G. W.

LETTER MCCLXXXVII.
To the Reverend Mr. G――.

Greenock, June 4, 1763.

S TRANGE! that I should not see one whom I so dearly love. Dear
Mr. S―― will tell you the reasons. I expect to be called every
moment. God bless and reward you and yours. The diploma was
sent to Edinburgh to be signed by Mr. Trail, but hath miscarried. I
wrote to Mr. Hamilton to send it by the Diligence, which is to sail in
about six weeks to Boston. Expecting to be called every moment, I
can only hasten to subscribe myself, reverend and very dear Sir,
 Ever yours, &c. &c. in Jesus,

G. W.

LETTER MCCLXXXVIII.
To Mr. S―― S――.

At Sea, July 15, 1763.

My very dear Friend,

I HOPE that this will find you and yours prospering both in soul and
body. It leaves me looking towards Virginia but only as an
harbour in my way to an infinitely better port, from whence I shall
never put out to sea again. Through mercy I have been surprizingly
kept up during the voyage, long but not tedious. Jesus hath made
the ship a Bethel, and I enjoyed that quietness which I have in vain
sought after for some years on shore. Not an oath to be heard even
in the greatest hurry. All hath been harmony and love. But my
breath is short, and I have little hopes, since my late relapse, of
much further public usefulness. A few exertions, like the last
struggles of a dying man, or glimmering flashes of a taper just
burning out, is all that can be expected from me. But blessed be
God, the taper will be lighted up again in heaven. The sun, when
setting here, only sets to rise in another clime. Such is the death of
all God’s saints. Why then should we be afraid? Why should we not
rather by faith be looking through the windows of mortality, and
daily crying, “Why are his chariot wheels so long in coming?” We had
need of patience, especially when the evil days of sickness and
declining age come. But we serve a Master who will not forsake his
servants when grey headed. When heart and flesh fail, God, even
our God in Christ, will be our portion and confidence for ever. Does
my dear Mr. S―― repent that he served and worked for Him when
young? Is dear Mrs. S―― sorrowful that he was the God of her
youth? Or is Miss now thinking that she hath lately made a wrong
choice? No, no: I will venture to answer for them all. Let us,
therefore, love our Master, and not go from him. Who knows but our
latter end may yet increase? If not in public usefulness, Lord Jesus,
let it be in inward heart-holiness, that we may daily ripen for the full
enjoyment of thyself in heaven! I know who says, Amen; I add
Amen, and Amen! and so subscribe myself, with ten thousand
thanks for all favours, my dear friends,

Yours, &c. &c. in our Jesus,

G. W.

August 24.

P. S. Since writing the above, we have been exercised by contrary

winds, thunders, lightenings, &c. but out of all the Lord hath brought
us, and we came within the Cape last night. Help me to praise him,
O my friends.
 LETTER MCCLXXXIX.
To Mr. P――ks.

Within Virginia-Cape, August 24, 1763.

My dear Mr. P――ks,

I FULLY purposed to write to you before my embarkation for

America, but sickness prevented. However, I dearly love you,
and often remember you before his throne, who I am persuaded
hath loved and given himself for you. This he hath told you, and
assured you of again and again by his blessed word and Spirit. Be
not therefore faithless, but believing. O that this may find you
rejoicing with that joy which is unspeakable and full of glory. It
leaves me longing for that blissful state, where sorrow and sighing
will flee away. There, there shall we meet, and in spite of all the
suggestions of Satan, and the desperate wickedness of our own
deceitful hearts, ere long join in singing the song of Moses and the
Lamb. Faithful is he that hath promised, who also will do it. Last
night, but not till then, we cast anchor after near a twelve weeks
passage. The last six weeks were very trying to my shattered bark.
But Jesus is All in All. Help, help to praise him. To his infinite and
never-failing mercy do I commend you, as being, for his great
name’s sake, my dear Mr. P――ks,

Yours most affectionately,

G. W.
 LETTER MCCXC.
To all my dear Tabernacle Hearers, that love the Lord Jesus
Christ in Sincerity.

Virginia, September 1, 1763.

Dearly Beloved in the Lord,

T HOUGH absent in body, the Searcher of hearts knows that I have

been present with you in spirit ever since I left London. Glad,
very glad was I to hear from time to time whilst ashore, that the
shout of a king was among you; and it was my continual prayer
whilst at sea, that the glory of the Lord may so fill the Tabernacle,
that all who come to hear the word, may be constrained to say,
“Surely God is in this place.” I doubt not of your wrestling in my
behalf. Certainly it must be in answer to your cryings unto the Lord,
that I have been dealt with so bountifully. For some weeks I was
enabled to preach once a day when in Scotland, and I trust not
without some divine efficacy. But my late disorder kept me silent for
some weeks afterwards, and put me upon thinking sometimes, that
my intended voyage would be retarded, at least for one year longer.
Having obtained a little more bodily strength, I ventured upon the
mighty waters, and thanks, eternal thanks to a never-failing
Redeemer, I have not been laid by an hour through sickness since I
came on board. Every thing hath been providentially ordered,
suitable to my low estate. A large and commodious cabbin, a kind
Captain, and a most orderly and quiet ship’s company, who gladly
attended when I had breath to preach. Scarce an oath have I heard
upon deck, during a twelve weeks voyage; and such a stillness
through the whole ship, both on week days and the Lord’s-day, as
hath from time to time surprized me. Some concern hath appeared,
but of what kind or duration the event alone can discover. The
spiritual bread hath been cast on the waters: who knows but it may
be found after many days. How it shall please my all-bountiful
Master to dispose of me when I get on shore, you shall know
hereafter. All that I can say is, (if I know any thing of my
unspeakably deceitful, and desperately wicked heart) Lord Jesus,

A life that all things casts behind,

Springs forth obedient to thy call;

A heart, that no desire can move,

But still t’adore, resign, and love,

Give me, my Lord, my life, my all!

You will not forget to persevere in praying for a poor, worthless, but
willing pilgrim, who dearly loves you, and daily rejoices in the
pleasing reflection, that he shall ere long meet you in a better world,
where the inhabitants shall no more say, “I am sick.” Blessed
prospect! Surely on the very mentioning it, you will break forth in
singing,

Rejoice, the Lord is king, &c.

I will not interrupt you. Adieu. The Lord Jesus be with your spirits.
Only when you have done singing, my dear fellow-labourers, my
dear Tabernacle-hearers, forget not to subjoin at least one petition,
that whether absent or present, Jesus may be more and more
precious to,

Your affectionate friend, and willing servant, for his great

name’s sake,

G. W.
 LETTER MCCXCI.
To all my dear Tottenham-Court Hearers, that love the Lord
Jesus Christ in Sincerity.

Virginia, September 1, 1763.

Dearly Beloved in the Lord,

T HOUGH less than the least of all, and unworthy, utterly unworthy
the notice of any, yet I cannot help thinking, but for Christ’s
sake you will be glad to hear of the goodness of the Lord extended
towards me since my departure from London. Surely it was trying, to
leave so many at each end of the town, who, I hope, will be my joy
and crown of rejoicing in the great day. Indeed, after being taken ill
of my old disorder at Edinburgh, and remaining near six weeks silent
in Scotland, I thought of seeing you soon again: but having obtained
help, I embarked, for the eleventh time, in the ship Fanny; and
though we have had a long and trying, yet, blessed be God, it hath
not been an unprofitable voyage. Often, often have I thought of my
dear London friends, when I guessed they were assembled together;
and as often prayed, when I knew they were retired to rest, that he
that keepeth Israel, and neither slumbereth nor sleepeth, would
watch over them, and make their very dreams devout. How I am to
be disposed of when on dry land, is best known to Him whose I am,
and whom I desire to serve in preaching the gospel of his dear Son.
Had I strength equal to my will, I could fly from pole to pole.
Though wearied, and now almost worn out, indeed and indeed I am
not weary of my blessed Master’s service. O love him, love him, for
he is a good Master, and doth not leave us when our strength
faileth. Make him your portion, and he will be your confidence for
ever. According to my present views, if able to do any thing for you,
through his leave I hope to see you again next year. In the mean
while, as long as I have breath to draw, it shall be my heart’s desire