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Ahmet Bindal

Fundamentals
of Computer
Architecture
and Design
Ahmet Bindal

Fundamentals
of Computer
Architecture and Design

123
Dr. Ahmet Bindal
Computer Engineering Department
San Jose State University
San Jose, CA, USA

The Solutions Manual for instructors can be found at

http://www.springer.com/us/book/9783319258096

ISBN 978-3-319-25809-6 ISBN 978-3-319-25811-9 (eBook)

DOI 10.1007/978-3-319-25811-9

Library of Congress Control Number: 2016960285

© Springer International Publishing Switzerland 2017

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or
part of the material is concerned, specifically the rights of translation, reprinting, reuse of
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The use of general descriptive names, registered names, trademarks, service marks, etc. in this
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exempt from the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in
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Printed on acid-free paper

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The registered company is Springer International Publishing AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
For my mother who always showed me the right path…
Preface

This book is written for young professionals and graduate students

who have prior logic design background and want to learn how to use
logic blocks to build complete systems from design specifications.
My two-decade-long industry experience has taught me that engineers
are “shape-oriented” people and that they tend to learn from charts and
diagrams. Therefore, the teaching method I followed in this textbook
caters this mind set: a lot of circuit schematics, block diagrams, timing
diagrams, and examples supported by minimal text.
The book has eight chapters. The first three chapters give a complete
review of the logic design principles since rest of the chapters signifi-
cantly depend on this review. Chapter 1 concentrates on the combina-
tional logic design. It describes basic logic gates, De Morgan’s theorem,
truth tables, and logic minimization. This chapter uses these key con-
cepts in order to design mega cells, namely various types of adders and
multipliers. Chapter 2 introduces sequential logic components, namely
latches, flip-flops, registers, and counters. It introduces the concept of
timing diagrams to explain the functionality of each logic block. The
Moore and Mealy-type state machines, counter–decoder-type con-
trollers, and the construction of simple memories are also explained in
this chapter. Chapter 2 also illustrates the design process: how to develop
architectural logic blocks using timing diagrams, and how to build a
controller from a timing diagram to guide data flow. Chapter 3 focuses
on the review of asynchronous logic design, which includes state defi-
nitions, primitive flow tables, and state minimization. Racing conditions
in asynchronous designs, how to detect and correct them are also
explained in this chapter. The chapter ends with designing an important
asynchronous timing block: the C element (or the Mueller element), and
it describes an asynchronous timing methodology that leads to a com-
plete design using timing diagrams.

vii
viii Preface

From Chapter 4 to Chapter 8, computer architecture-related topics

are covered. Chapter 4 examines a very essential system element:
system bus and communication protocols between system modules.
This chapter defines the bus master and the bus slave concepts and
examines their bus interfaces. Read and write bus cycles and protocols,
bus handover and arbitration are also examined in this chapter. System
memories, namely Static Random Access Memory (SRAM),
Synchronous Dynamic Random Access Memory (SDRAM),
Electrically-Erasable-Programmable-Read-Only-Memory (E2PROM)
and Flash memory are examined in Chapter 5. This chapter also shows
how to design bus interface for each memory type using timing dia-
grams and state machines. Chapter 6 is all about the design of a simple
Reduced Instruction Set Computer (RISC) for central processing. The
chapter starts with introducing a simple assembly instruction set and
building individual hardware for each instruction. As other instructions
are introduced to the design, techniques are shown how to integrate
additional hardware to the existing CPU data-path to be able to execute
multiple instructions. Fixed-point and floating-point Arithmetic Logic
Units (ALU) are also studied in this chapter. Structural, data and pro-
gram control hazards, and the required hardware to avoid them are
shown. This chapter ends with the operation of various cache archi-
tectures, cache read and write protocols, and the functionality of
write-through and write-back caches. The design of system peripherals,
namely Direct Memory Access (DMA), interrupt controller, system
timers, serial interface, display adapter and data controllers are covered
in Chapter 7. The design methodology to construct data-paths with
timing diagrams in Chapter 2 is closely followed in this chapter in order
to design the bus interface for each peripheral. Chapter 8 describes the
Field-Programmable Gate array (FPGA), and the fundamentals of data
driven processors as special topics.
At the end of the book, there is a small appendix that introduces the
Verilog language. Verilog is a widely used Hardware Design
Language (HDL) to build and verify logic blocks, mega cells and
systems. Interested readers are encouraged to go one step beyond and
learn system Verilog to be able to verify large logic blocks.

Dr. Ahmet Bindal

Computer Engineering Department
San Jose State University
San Jose, CA, USA
Contents

1 Review of Combinational Circuits . . . . . . . . . . . . . ... 1

1.1 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . ... 2
1.2 Boolean Algebra. . . . . . . . . . . . . . . . . . . . . . ... 8
1.3 Designing Combinational Logic Circuits
Using Truth Tables . . . . . . . . . . . . . . . . . . . . ... 11
1.4 Combinational Logic Minimization—Karnaugh
Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 14
1.5 Basic Logic Blocks . . . . . . . . . . . . . . . . . . . . ... 20
1.6 Combinational Mega Cells . . . . . . . . . . . . . . . ... 29

2 Review of Sequential Logic Circuits. . . . . . . . . . . . . . . 67

2.1 D Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.2 Timing Methodology Using D Latches . . . . . . . . . 69
2.3 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4 Timing Methodology Using D Flip-Flops . . . . . . . 72
2.5 Timing Violations . . . . . . . . . . . . . . . . . . . . . . . . 73
2.6 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.7 Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.9 Moore Machine . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.10 Mealy Machine . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.11 Controller Design: Moore Machine
Versus Counter-Decoder Scheme . . . . . . . ...... 90
2.12 Memory . . . . . . . . . . . . . . . . . . . . . . . . ...... 94
2.13 A Design Example Using Sequential Logic
and Memory . . . . . . . . . . . . . . . . . . . . . ...... 97

3 Review of Asynchronous Logic Circuits . . . . . . . . . . . . 113

3.1 S-R Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.2 Fundamental-Mode Circuit Topology . . . . . . . . . . 114

ix
x Contents

3.3 Fundamental-Mode Asynchronous

Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.4 Asynchronous Timing Methodology . . . . . . . . . . . 123
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4 System Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.1 Parallel Bus Architectures . . . . . . . . . . . . . . . . . . 133
4.2 Basic Write Transfer . . . . . . . . . . . . . . . . . . . . . . 138
4.3 Basic Read Transfer . . . . . . . . . . . . . . . . . . . . . . 140
4.4 Bus Master Status Change . . . . . . . . . . . . . . . . . . 142
4.5 Bus Master Handshake . . . . . . . . . . . . . . . . . . . . 145
4.6 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.7 Bus Master Handover . . . . . . . . . . . . . . . . . . . . . 148
4.8 Serial Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5 Memory Circuits and Systems . . . . . . . . ........... 169

5.1 Static Random Access Memory . . . ........... 170
5.2 Synchronous Dynamic Random
Access Memory . . . . . . . . . . . . . . ........... 179
5.3 Electrically-Erasable-Programmable-
Read-Only-Memory . . . . . . . . . . . . . . . . . . . . . . 201
5.4 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5 Serial Flash Memory . . . . . . . . . . . . . . . . . . . . . . 253
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

6 Central Processing Unit . . . . . . . . . . . . . . . . . . . . ... 275

6.1 RISC Instruction Formats. . . . . . . . . . . . . . . . ... 275
6.2 CPU Data-Path. . . . . . . . . . . . . . . . . . . . . . . ... 277
6.3 Fixed-Point Register-to-Register
Type ALU Instructions . . . . . . . . . . . . . . . . . . . . 280
6.4 Fixed-Point Immediate Type ALU Instructions . . . . 292
6.5 Data Movement Instructions. . . . . . . . . . . . . . . . . 298
6.6 Program Control Instructions . . . . . . . . . . . . . . . . 302
6.7 Design Example I: A Fixed-Point CPU
with Four Instructions . . . . . . . . . . . . . . . . . . ... 308
6.8 Design Example II: A Fixed-Point CPU
with Eight Instructions . . . . . . . . . . . . . . . . . ... 313
6.9 Floating-Point Instructions . . . . . . . . . . . . . . . ... 316
6.10 Floating-Point. . . . . . . . . . . . . . . . . . . . . . . . ... 317
Contents xi

6.11 Floating-Point Adder . . . . . . . . . . . . . . . . . . . . .. 322

6.12 Floating-Point Multiplier . . . . . . . . . . . . . . . . . .. 324
6.13 A RISC CPU with Fixed
and Floating-Point Units . . . . . . . . . . . . . . . . . . . 325
6.14 Structural Hazards. . . . . . . . . . . . . . . . . . . . . . . . 327
6.15 Data Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.16 Program Control Hazards. . . . . . . . . . . . . . . . . . . 333
6.17 Handling Hazards in a Five-Stage RISC CPU:
An Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.18 Handling Hazards in a Four-Stage RISC CPU . . . . 339
6.19 Handling Hazards in a Three-Stage RISC CPU. . . . 340
6.20 Multi-cycle ALU and Related Data Hazards . . . . . . 342
6.21 Cache Topologies . . . . . . . . . . . . . . . . . . . . . . . . 346
6.22 Cache Write and Read Structures . . . . . . . . . . . . . 349
6.23 A Direct-Mapped Cache Example . . . . . . . . . . . . . 351
6.24 Write-Through and Write-Back Cache Structures
in Set-Associative Caches . . . . . . . . . . . . . . . . .. 354
6.25 A Two-Way Set-Associative Write-Through
Cache Example . . . . . . . . . . . . . . . . . . . . . . . .. 355
6.26 A Two-Way Set-Associative Write-Back
Cache Example . . . . . . . . . . . . . . . . . . . . . . . .. 358
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 375

7 System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

7.1 Overall System Arcitecture. . . . . . . . . . . . . . . . . . 377
7.2 Direct Memory Access Controller . . . . . . . . . . . . . 378
7.3 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . 387
7.4 Serial Transmitter and Receiver Interface . . . . . . . . 399
7.5 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
7.6 Display Adaptor . . . . . . . . . . . . . . . . . . . . . . . . . 414
7.7 Data Converters . . . . . . . . . . . . . . . . . . . . . . . . . 425
7.8 Digital-to-Analog Converter (DAC). . . . . . . . . . . . 437
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

8 Special Topics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

8.1 Field-Programmable-Gate Array . . . . . . . . . . . . . . 455
8.2 Data-Driven Processors . . . . . . . . . . . . . . . . . . . . 473
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
xii Contents

Appendix: An Introduction to Verilog Hardware

Design Language. . . . . . . . . . . . . . . . . . . . . . . 491

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
About the Author

Ahmet Bindal received his M.S. and Ph.D.

degrees in Electrical Engineering Depart-
ment from the University of California, Los
Angeles, CA. His doctoral thesis was the
material characterization in High Electron
Mobility (HEMT) GaAs transistors. During
his graduate studies, he was a research
associate and a technical consultant for
Hughes Aircraft Co. In 1988, he joined the
technical staff of IBM Research and Devel-
opment Center in Fishkill, NY, where he worked as a device design
and characterization engineer. He developed asymmetrical MOS
transistors and ultrathin silicon on insulator (SOI) technologies for
IBM. In 1993, he transferred to IBM at Rochester, MN, as a senior
circuit design engineer to work on the floating-point unit for the
AS-400 main frame processor. He continued his circuit design career
at Intel Corporation in Santa Clara, CA, where he designed 16-bit
packed multipliers and adders for the MMX unit in Pentium II pro-
cessors. In 1996, he joined Philips Semiconductors in Sunnyvale, CA,
where he was involved in the designs of instruction/data caches and
various SRAM modules for the TriMedia processor. His involvement
with VLSI architecture also started in Philips Semiconductors and led
to the design of the Video-Out unit for the same processor. In 1998, he
joined Cadence Design Systems as a VLSI architect and directed a
team of engineers to design self-timed asynchronous processors. After
approximately 20 years of industry work, he joined the computer
engineering faculty at San Jose State University in 2002. His current
research interests range from nano-scale electron devices to robotics.

xiii
xiv About the Author

Dr. Bindal has over 30 scientific journal and conference publications

and 10 invention disclosures with IBM. He currently holds three US
patents with IBM and one with Intel Corporation. On the light side of
things, Dr. Bindal is a model aircraft builder and an avid windsurfer
for more than 30 years.
 Review of Combinational Circuits
1

Logic gates are the essential elements in digital design, and ultimately constitute the building
blocks for digital systems. A good understanding in designing complex logic blocks from
primitive logic gates, and mastering the design tools and techniques that need to be incor-
porated in the design process is a requirement for the reader before moving to the details of
computer architecture and design.
This chapter starts with defining the logic gates and the concept of truth table which then
leads to the implementation of basic logic circuits. Later in the chapter, the concept of
Karnaugh maps is introduced in order to minimize gate count, thereby completing the basic
requirements of combinational logic design. Following the minimization techniques, various
fundamental logic blocks such as multiplexers, encoders, decoders and one-bit adders are
introduced so that they can be used to construct larger scale combinational logic circuits. The
last section of this chapter is dedicated to the design of mega cells. These include different
types of adders such as ripple-carry adder, carry-look-ahead adder, carry-select adder, and
the combination of all three types depending on the goals of the design: gate count, circuit
speed and power consumption. Subtractors, linear and barrel shifters, array and Booth
multipliers constitute the remaining sections of this chapter.
It is vital for the reader to also invest time to learn a hardware design language such as
Verilog while studying this chapter and the rest of the chapters in this book. A simulation
platform incorporating Verilog and a set of tools that work with Verilog such as design
synthesis, static timing analysis, and verification is an effective way to check if the intended
design is correct or not. There is nothing more valuable than trying various design ideas on a
professional design environment, and understanding what works and what does not while
learning from your mistakes. An appendix introducing the basic principles of Verilog is
included at the end of this book for reference.

© Springer International Publishing Switzerland 2017 1

A. Bindal, Fundamentals of Computer Architecture and Design,
DOI 10.1007/978-3-319-25811-9_1
2 1 Review of Combinational Circuits

1.1 Logic Gates

AND gate

To understand how AND gate functions, assume that the output, OUT, in Fig. 1.1 is at logic
0 when both switches, A and B, are open. Unless both A and B close, the output stays at
logic 0.

OUT

Fig. 1.1 Switch representation of a two-input AND gate

A two-input AND gate functions similarly to the circuit in Fig. 1.1. If any of the two
inputs, A or B, is at logic 0 in the AND gate in Fig. 1.2, the gate produces a logic 0 output at
OUT. Both inputs of the gate must be equal to logic 1 in order to produce an output at logic 1.
This behavior is tabulated in Table 1.1, which is called a “truth table”.

A
OUT
B

Fig. 1.2 Two-input AND gate symbol

Table 1.1 Two-input AND gate truth table

A B OUT

0 0 0
0 1 0
1 0 0
1 1 1
1.1 Logic Gates 3

The functional representation of the two-input AND gate is:

OUT ¼ A : B

Here, the symbol “.” between inputs A and B represents the AND-function.

OR gate

Now, assume a parallel connectivity between switches A and B as shown in Fig. 1.3. OUT
becomes logic 1 if one of these switches closes; otherwise the output will stay at logic 0.

A B

OUT

Fig. 1.3 Switch representation of two-input OR gate

A two-input OR gate shown in Fig. 1.4 functions similarly to the circuit in Fig. 1.3. If any
of the two inputs is at logic 1, the gate produces an output, OUT, at logic 1. Both inputs must
be equal to logic 0 in order to produce a logic 0 output. This behavior is tabulated in the truth
table, Table 1.2.

A
OUT
B

Fig. 1.4 Two-input OR gate symbol

Table 1.2 Two-input OR gate truth table

A B OUT

0 0 0
0 1 1
1 0 1
1 1 1
4 1 Review of Combinational Circuits

The functional representation of the two-input OR gate is:

OUT ¼ A þ B

Here, the symbol “+” between inputs A and B signifies the OR-function.

Exclusive OR gate

A two-input Exclusive OR gate, XOR gate, is shown in Fig. 1.5. The XOR gate produces a
logic 0 output if both inputs are equal. Therefore, in many logic applications this gate is used
to compare the input logic levels to see if they are equal. The functional behavior of the gate
is tabulated in Table 1.3.

A
OUT
B

Fig. 1.5 Two-input XOR gate symbol

Table 1.3 Two-input XOR gate truth table

A B OUT

0 0 0
0 1 1
1 0 1
1 1 0

The functional representation of the two-input XOR gate is:

OUT = A  B

Here, the “⊕” symbol between inputs A and B signifies the XOR-function.

Buffer

A buffer is a single input device whose output is logically equal to its input. The only use of
this gate is to be able to supply enough current to the capacitive load created by a multitude of
logic gates connected to its output. The logical representation of this gate is shown in Fig. 1.6.

IN OUT

Fig. 1.6 Buffer symbol

1.1 Logic Gates 5

Complementary Logic Gates

All basic logic gates need to have complemented forms in logic design. If a single input
needs to be complemented, an inverter shown in Fig. 1.7 is used. The inverter truth table is
shown in Table 1.4.

IN OUT

Fig. 1.7 Inverter symbol

Table 1.4 Inverter truth table

IN OUT

0 1
1 0

The functional representation of the inverter is:

OUT ¼ IN

Here, the “-” symbol on top of the input, IN, represents the complement-function.
The complemented form of two-input AND gate is called two-input NAND gate, where “N”
signifies negation. The logic representation is shown in Fig. 1.8, where a circle at the output of
the gate means complemented output. The truth table of this gate is shown in Table 1.5. Note
that all output values in this table are exact opposites of the values given in Table 1.1.

A
OUT
B

Fig. 1.8 Two-input NAND gate symbol

Table 1.5 Two-input NAND gate truth table

A B OUT

0 0 1
0 1 1
1 0 1
1 1 0
6 1 Review of Combinational Circuits

The functional representation of the two-input NAND gate is:

OUT ¼ A : B

Similar to the NAND gate, the two-input OR and the two-input XOR gates have com-
plemented configurations, called the two-input NOR and the two-input XNOR gates,
respectively.
The symbolic representation and truth table of a two-input NOR gate is shown in Fig. 1.9
and Table 1.6, respectively. Again, all the outputs in Table 1.6 are the exact complements of
the outputs in Table 1.2.

A
OUT
B

Fig. 1.9 Two-input NOR gate symbol

Table 1.6 Two-input NOR gate truth table

A B OUT

0 0 1
0 1 0
1 0 0
1 1 0

The functional representation of the two-input NOR gate is:

OUT ¼ A þ B

The symbolic representation and truth table of a two-input XNOR gate is shown in
Fig. 1.10 and Table 1.7, respectively. This gate, like its counterpart the two-input XOR gate,
is often used to detect if input logic levels are equal.

A
OUT
B

Fig. 1.10 Two-input XNOR gate symbol

Table 1.7 Two-input XNOR gate truth table

A B OUT

0 0 1
0 1 0
1 0 0
1 1 1
1.1 Logic Gates 7

The functional representation of the two-input XNOR gate is:

OUT ¼ A  B

Tri-State Buffer and Inverter

It is often necessary to create an open circuit between the input and the output of a logic gate
if the gate is not enabled. This need creates two more basic logic gates, the tri-state buffer
and tri-state inverter.
The tri-state buffer is shown in Fig. 1.11. Its truth table in Table 1.8 indicates continuity
between the input and the output terminals if the control input, EN, is at logic 1. When EN is
lowered to logic 0, an open circuit exists between the IN and the OUT terminals, which is
defined as high impedance state (HiZ).

IN OUT

EN

Fig. 1.11 Tri-state buffer symbol

Table 1.8 Tri-state buffer truth table

EN IN OUT

0 0 HiZ
0 1 HiZ
1 0 0
1 1 1

The tri-state inverter is shown in Fig. 1.12 along with its truth table in Table 1.9. This
gate behaves like an inverter when EN input is at logic 1. However, when EN is lowered to
logic 0, its output disconnects from its input.

IN OUT

EN

Fig. 1.12 Tri-state inverter symbol

8 1 Review of Combinational Circuits

Table 1.9 Tri-state inverter truth table

EN IN OUT

0 0 HiZ
0 1 HiZ
1 0 1
1 1 0

The control input, EN, to tri-state buffer and inverter can also be complemented in order to
produce an active-low enabling scheme.
The tri-state buffer with the active-low enable input in Fig. 1.13 creates continuity when
EN = 0.

IN OUT

EN

Fig. 1.13 Tri-state buffer symbol with complemented enable input

The tri-state inverter with the active-low input in Fig. 1.14 also functions like an inverter
when EN is at logic 0, but its output becomes HiZ when EN is changed to logic 1.

IN OUT

EN

Fig. 1.14 Tri-state inverter symbol with complemented enable input

1.2 Boolean Algebra

It is essential to be able to reconfigure logic functions to suit our design goals. Logical
reconfigurations may be as simple as regrouping the inputs to a single gate or comple-
menting the inputs of several gates to reach a design objective.
The identity, commutative, associative, distributive laws and the DeMorgan’s negation
rules are used to perform logical manipulations. Table 1.10 tabulates these laws.
1.2 Boolean Algebra 9

Table 1.10 Identity, commutative, associative, distributive and DeMorgan’s rules

A.1=A
A.0=0
A.A=A
A.A=0
Identity
A+1=1
A+0=A
A+A=A
A+A=1
A=A

A.B=B.A
Commutative
A+B=B+A

A . (B . C) = (A . B) . C
Associative
A + (B + C) = (A + B) + C

A . (B + C) = A . B + A . C
Distributive
A + B . C = (A + B) . (A + C)

A.B=A+B
DeMorgan’s
A+B=A.B

Example 1.1: Reduce OUT ¼ A : B : C þ A : B : C þ A : B using algebraic rules.

OUT ¼ A : B : C þ A : B : C þ A : B
¼ A : C : ðB þ BÞ þ A : B
¼ A : (C þ BÞ

Example 1.2: Reduce OUT ¼ A þ A : B using algebraic rules.

OUT ¼ A þ A : B
¼ ðA þ AÞ : ðA þ BÞ
¼ A þ B
10 1 Review of Combinational Circuits

Example 1.3: Reduce OUT ¼ A : B þ A : C þ B : C using algebraic rules.

OUT ¼ A : B þ A : C þ B : C
¼ A : B þ A : C þ B : C : ðA þ AÞ
¼ A : B þ A: C þ A: B : C þ A: B : C
¼ A : B : ð1 þ CÞ þ A : C : ð1 þ B)
¼A:BþA:C

Example 1.4: Reduce OUT ¼ ðA þ BÞ : ðA þ C) using algebraic rules.

OUT ¼ ðA þ BÞ : ðA þ C)
¼A : A þ A : C þ A : B þ B : C
¼A : C þ A : B þ B : C
¼ A : C þ A : B þ B : C : ðA þ AÞ
¼A : C þ A : B þ A : B : C þ A : B : C
¼ A : C : ð1 þ BÞ þ A : B : ð1 þ CÞ
¼A : C þ A : B

Example 1.5: Convert OUT ¼ ðA þ BÞ : C : D into an OR-combination of two-input

AND gates using algebraic laws and DeMorgan’s theorem.

OUT ¼ ðA þ BÞ : C : D
¼ ðA þ BÞ : ðC þ DÞ
¼A:CþA:DþB:CþB:D

Example 1.6: Convert OUT ¼ A : B þ C : D into an AND-combination of two-input OR

gates using algebraic laws and DeMorgan’s theorem.

OUT ¼ A : B þ C : D
¼A:BþC:D
¼ ðA þ BÞ : ðC þ DÞ
1.3 Designing Combinational Logic Circuits Using Truth Tables 11

1.3 Designing Combinational Logic Circuits Using Truth Tables

A combinational logic circuit is a cascaded form of basic logic gates without any feedback
from the output to any of its inputs. The logic function is obtained from a truth table that
specifies the complete functionality of the digital circuit.
Example 1.7: Using the truth table given in Table 1.11 determine the output function of the
digital circuit.

Table 1.11 An arbitrary truth table with four inputs

A B C D OUT

0 0 0 0 1

0 0 0 1 1
0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1
0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1
1 0 1 0 1

1 0 1 1 0

1 1 0 0 0

1 1 0 1 0
1 1 1 0 0

1 1 1 1 0

The output function can be expressed either as the OR combination of AND gates or the
AND combination of OR gates.
If the output is expressed in terms of AND gates, all output entries that are equal to one in
the truth table must be grouped together as a single OR gate.
12 1 Review of Combinational Circuits

OUT ¼ A : B : C : D þ A : B : C : D þ A : B : C : D þ A : B : C : D
þA:B:C:DþA:B:C:DþA:B:C:D

This expression is called the Sum Of Products (SOP), and it contains seven terms each
of which is called a “minterm”. In the first minterm, each A, B, C and D input is com-
plemented to produce OUT = 1 for the A = B = C = D = 0 entry of the truth table. Each of
the remaining six minterms also complies with producing OUT = 1 for their respective input
entries.
The resulting combinational circuit is is shown Fig 1.15.

A
B
C
D
A
B
C
D
A
B
C
D
A
B
OUT
C
D
A
B
C
D
A
B
C
D
A
B
C
D

Fig. 1.15 AND-OR logic representation of the truth table in Table 1.11

If the output function needs to be expressed in terms of OR gates, all the output entries
that are equal to zero in the truth table must be grouped as a single AND gate.
1.3 Designing Combinational Logic Circuits Using Truth Tables 13

OUT ¼ ðA þ B þ C þ DÞ : (A þ B þ C þ DÞ : ðA þ B þ C þ D)
: ðA þ B þ C þ DÞ : ðA þ B þ C þ DÞ : ðA þ B þ C þ DÞ
: ðA þ B þ C þ DÞ : ðA þ B þ C þ D) : ðA þ B þ C þ DÞ

This expression is called the Product Of Sums (POS), and it contains nine terms each of
which is called a “maxterm”. The first maxterm produces OUT = 0 for the ABCD = 0011
entry of the truth table. Since the output is formed with a nine-input AND gate, the values of
the other maxterms do not matter to produce OUT = 0. Each of the remaining eight max-
terms generates OUT = 0 for their corresponding truth table input entries.
The resulting combinational circuit is shown in Fig. 1.16.

A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
OUT
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D

Fig. 1.16 OR-AND logic representation of the truth table in Table 1.11
14 1 Review of Combinational Circuits

1.4 Combinational Logic Minimization—Karnaugh Maps

One of the most useful tools in logic design is the use of Karnaugh maps (K-map) to
minimize combinational logic functions.
Minimization can be performed in two ways. To obtain the SOP form of a minimized
logic function, logic 1 entries of the truth table must be grouped together in the K-map. To
obtain the POS form of a minimized logic function, logic 0 entries of the truth table must be
grouped together in the K-map.
Example 1.8: Using the truth table in Table 1.12, determine the minimized SOP and POS
output functions. Prove them to be identical.

Table 1.12 An arbitrary truth table with three inputs

A B C OUT

0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

The SOP function is formed by grouping logic 1s in Fig. 1.17 to obtain the minimized
output function, OUT.

OUT
AB
C 00 01 11 10

0 1 1 0 1

1 1 0 0 1

Fig. 1.17 K-map of the truth table in Table 1.12 to determine SOP

Grouping 1s takes place among neighboring boxes in the K-map where only one variable
is allowed to change at a time. For instance, the first grouping of 1s combines the ABC = 000
and ABC = 010 entries as they are in the neighboring boxes. Only B changes from logic 0 to
logic 1 while A and C stay constant at logic 0. To obtain OUT = 1, both A and C need to be
complemented; this produces the first term, A : C, for the output function. Similarly, the
second grouping of 1s combines the neighboring boxes, ABC = 000, 001, 100 and 101,
where both A and C change while B stays constant at logic 0. To obtain OUT = 1, B needs to
be complemented; this generates the second term, B, for the output function.
1.4 Combinational Logic Minimization—Karnaugh Maps 15

This means that either the term A : C or B makes OUT equal to logic 1. Therefore, the
minimized output function, OUT, in the SOP form is:

OUT ¼ B þ A : C

Grouping 0s produces the minimized POS output function as shown in Fig. 1.18.

OUT
AB
C 00 01 11 10

0 1 1 0 1

1 1 0 0 1

Fig. 1.18 K-map of the truth table in Table 1.12 to determine POS

This time, the first grouping of 0s combines the boxes, ABC = 011 and 111, where A
changes from logic 0 to logic 1 while B and C stay constant at logic 1. This grouping targets
OUT = 0, which requires both B and C to be complemented. As a result, the first term of the
output function, B þ C, is generated. The second grouping combines ABC = 110 and 111
where C changes from logic 0 to logic 1 while A and B stay at logic 1. To obtain OUT = 0,
both A and B need to be complemented. Consequently, the second term, A þ B, forms.
Therefore, either B þ C or A þ B should produce OUT = 0, resulting the following POS
function.

OUT ¼ ðB þ CÞ : ðA þ BÞ

To find out if the SOP and POS forms are identical to each other, we can manipulate the
POS expression above using the algebraic rules given earlier.

OUT ¼ ðB þ CÞ : ðA þ BÞ
¼ A:B þ B:B þ A:C þ B:C
¼A:BþBþA:CþB:C
¼ B : ðA þ 1 þ CÞ þ A : C
¼ B þ A :C

This is the SOP form of the output function derived above.

Example 1.9: Using the truth table in Example 1.7 determine the minimized SOP and POS
output functions.
To obtain the output function in SOP form, logic 1s in the K-map in Fig. 1.19 are grouped
together as shown below.
16 1 Review of Combinational Circuits

OUT
AB
CD 00 01 11 10

00 1 0 0 1

01 1 1 0 1

11 0 0 0 0

10 1 0 0 1

Fig. 1.19 K-map of the truth table in Table 1.11 to determine SOP

The minimized output function contains only three minterms compared to seven minterms
in Example 1.7. Also, the minterms are reduced to groups of two or three inputs instead of four.

OUT ¼ B : C þ A : C : D þ B : D

The resultant combinational circuit is shown in Fig. 1.20

B
C

A
C OUT
D

B
D

Fig. 1.20 Minimized logic circuit in SOP form from the K-map in Fig. 1.19

Further minimization can be achieved algebraically, which then reduces the number of
terms from three to two.

OUT ¼ B : ðC þ DÞ þ A : C : D

The corresponding combinational circuit is shown in Fig. 1.21.

1.4 Combinational Logic Minimization—Karnaugh Maps 17

B
C
D

OUT

A
C
D

Fig. 1.21 Logic circuit in Fig. 1.20 after algebraic minimizations are applied

To obtain the POS output function, logic 0s are grouped together as shown in Fig. 1.22.

OUT
AB
CD 00 01 11 10

00 1 0 0 1

01 1 1 0 1

11 0 0 0 0

10 1 0 0 1

Fig. 1.22 K-map of the truth table in Table 1.11 to determine POS

The minimized output function contains only three maxterms compared to nine in
Example 1.7. Also, the maxterms are reduced to groups of two inputs instead of four.

OUT ¼ ðC þ DÞ : ðA þ BÞ : ðB þ D)

The resultant combinational circuit is shown in Fig. 1.23

C
D

A
B OUT

B
D

Fig. 1.23 Minimized logic circuit in POS form from the K-map in Fig. 1.22
Exploring the Variety of Random
Documents with Different Content
 Kun tämä harkitsematon ja äkkipäinen menettely tov. Tarjuksen
taholta ei ollut herättämättä kiusallista huomiota koko
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 Tämän jälkeen jatkui iltaman suoritus enemmittä häiriöittä, ja vasta
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sikeimmässä unessaan, läksivät Pöllölän internaalit ja kommunistiset
solut itsekukin tyytyväisenä kulkemaan kotiansa kohti.
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