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C o m p u t e r Systems
Performance Evaluation
and Prediction
This Page Intentionally Left Blank
C o m p u t e r Systems
Performance Evaluation
and Prediction
Paul J. Fortier
Howard E. Michel
Digital PTess
An imprint of Elsevier Science
A m s t e r d a m • Boston • H e i d e l b e r g • L o n d o n • N e w Y o r k . O x f o r d • Paris • San Diego
San Francisco • Singapore • Sydney • Tokyo
Digital Press is an imprint of Hsevier Science.
No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the
prior written permission of the publisher.
Recognizing the importance of preserving what has been written, Elsevier Science prints its
books on acid-free paper whenever possible.
Fortier, Paul J.
Computer systems performance evaluation / Paul J. Fortier, Howard E. Michel.
p. c m .
ISBN 1-55558-260-5 (pbk. :alk. paper)
1. Computer systemsmEvaluation. 2. Computer systems~Reliability. I. Michel,
Howard. II. Title.
109876 543 2 1
Preface xi
I Introduction
I.I Evolution of computer systems architectures 2
1.2 Evolution of database systems 10
1.3 Evolution of operating systems 15
1.4 Evolution of computer networks 19
1.5 Need for performance evaluation 22
1.6 Role of performance evaluation in computer engineering 23
1.7 Overview of performance evaluation methods 24
1.8 Performance metrics and evaluation criteria 36
Probability 139
5.1 Random variables 149
5.2 Jointly distributed random variables 150
5.3 Probability distributions 150
5.4 Densities 152
5.5 Expectation 155
5.6 Some example probability distributions 163
5.7 Summary 177
7 Queuing T h e o r y 201
7.1 Queuing systems 201
7.2 Networks of queues 219
7.3 Estimating parameters and distributions 227
7.4 Computational methods for queuing network solutions 233
7.5 Summary 249
Contents ix
10 H a r d w a r e Testbeds, I n s t r u m e n t a t i o n , M e a s u r e m e n t ,
D a t a E x t r a c t i o n , and Analysis 305
10.1 Derivation of performance evaluation parameters 311
10.2 Network performance tests 315
10.3 General methods of data extraction 319
10.4 Testbed and model workloads 322
10.5 Experimental design 326
10.6 Data presentation 328
10.7 Summary 330
12 Analysis of C o m p u t e r A r c h i t e c t u r e s 345
12. I Introduction 345
I Contents
x Contents
References 495
Index 505
Preface
the concept of a pure birth and death process is developed, as are analysis
techniques. The chapter then delves into the Markov process and Markov
chains as they relate to the analysis of computer systems and their elements.
In Chapter 7, we introduce the concept of a queue and the analysis tech-
niques required to evaluate single queues and networks of queues. These
techniques are then developed into modeling techniques applied to com-
puter systems evaluation.
Chapter 8 introduces the concept of simulation modeling. The methods
for constructing simulation models from a description of an intended mod-
eled system are presented. The concepts of simulation events and timekeep-
ing are addressed, followed by the application of techniques to computer
systems analysis.
Chapter 9 introduces another analysis technique: Petri nets. The basic
elements comprising Petri nets are developed and then applied to modeling
aspects of computer systems. Fundamental Petri nets are described, as are
timed and general Petri nets.
Chapter 10 shows prospective designers or architects how to model
future systems configurations using present systems information. The chap-
ter shows how to instrument a system in order to extract and measure sys-
tems performance numbers. These measurements and data are then used in
development of analysis processes for defining present performance and
predicting future performance of computer systems and their components.
Chapter 11 aids the reader in determining what specific analysis tool is
best used to evaluate a computer system or component of interest. The
modeler is presented material to aid in determining when to use analytical
techniques, which technique to use, and when to use it. If analytical tech-
niques are not the best to use, the reader is advised how to select a simula-
tion modeling tool and when to apply it in analyzing a computer system.
Finally, the reader is given information regarding when and how to select
the appropriate operational analysis tool for measuring and modeling exist-
ing computer systems and components.
Chapters 12 through 15 provide analysis examples for specific computer
systems components. Computer architecture and component evaluation are
provided, as are operating systems, database systems, and network systems
modeling and analysis.
I Preface
This Page Intentionally Left Blank
I
Introduction
l 1
I/0 Processor ,,I Output [
I 'nput I Devices I
Devices I
and the processing capacity to manipulate the stored data. A processing unit
of a computer system consists of five main elements: the memory, an arith-
metic logic unit, an input unit, an output unit, and a control element. The
memory unit stores both the data for programs and the instructions of a
program that manipulates stored data.
The program's individual elements or instructions are fetched from the
memory one at a time and are interpreted by the control unit. The control
unit, depending on the interpretation of the instruction, determines what
computer operation to perform next. If the instruction requires no addi-
tional data, the control indicates to the arithmetic logic unit what operation
to perform and with what registers. (See Figure 1.1.)
If the instruction requires additional data, the control unit passes the
appropriate command to the memory (MAR, memory address register) to
fetch a data item from memory (MDR, memory data register) and to place
it in an appropriate register in the ALU (data register bank) (Figure 1.2).
lk
r
Figure 1.2
Low-level memory
Memory
access.
Array
ALU 1-"
$
Registers
I Chapter I
4 I. I Evolution of computer systems architectures
This continues until all required operands are in the appropriate registers of
the ALU. Once all operands are in place, the control unit commands the
ALU to perform the appropriate instruction--for example, multiplication,
addition, or subtraction. If the instruction indicated that an input or output
were required, the control element would transmit a word from the input
unit to the memory or ALU, depending on the instruction. If an output
instruction were decoded, the control unit would command the transmis-
sion of the appropriate memory word or register to the output channel indi-
cated. These five elements comprise the fundamental building blocks used
in the original von Neumann computer system and are found in most con-
temporary systems in some form or another.
A computer system is comprised of the five building blocks previously
described, as well as additional peripheral support devices, which aid in data
movement and processing. These basic building blocks are used to form the
general processing, control, storage, and input and output units that make
up modern computer systems. Devices typically are organized in a manner
that supports the application processing for which the computer system is
intended--for example, if massive amounts of data need to be stored, then
additional peripheral storage devices such as disks or tape units are required,
along with their required controllers or data channels.
To better describe the variations within architectures we will discuss
some details briefly--for example, the arithmetic logic unit (ALU) and the
control unit are merged together into a central processing unit, or CPU.
The CPU controls the flow of instructions and data in the computer sys-
tem. Memories can be broken down into hierarchies based on nearness to
the CPU and speed of access--for example, cache memory is small,
extremely fast memory used for instructions and data actively executing and
being used by the CPU. The primary memory is slower, but it is also
cheaper and contains more memory locations. It is used to store data and
instructions that will be used during the execution of applications presently
running on the CPU--for example, if you boot up your word processing
program on your personal computer, the operating system will attempt to
place the entire word processing program in primary memory. If there is
insufficient space, the operating system will partition the program into seg-
ments and pull them in as needed.
The portion of the program that cannot be stored in memory is main-
tained on a secondary storage device, typically a disk drive. This device has
a much greater storage capacity than the primary memory, typically costs
much less per unit of storage, and has data access times that are much
slower than the primary memory. An additional secondary storage device is
I. I Evolution of computer systems architectures 5
the tape drive unit. A tape drive is a simple storage device that can store
massive amounts of data~again, at less cost than the disk units but at a
reduced access speed. Other components of a computer system are input
and output units. These are used to extract data from the computer and
provide these data to external devices or to input data from the external
device. The external devices could be end-user terminals, sensors, informa-
tion network ports, video, voice, or other computers.
A computer system's architecture is constructed using basic building
blocks, such as CPUs, memories, disks, I/O, and other devices as needed.
In the following sections we will examine each of the components of a
computer system in more detail, as we examine how these devices can be
interconnected to support data processing applications.
1.1.1 CPU a r c h i t e c t u r e s
The central processing unit (CPU) is the core of a computer system and
consists of the arithmetic logic unit (ALU) and the control unit. The ALU
can come in a variety of configurations~from a single simple unit, up to
extremely complex units that perform complex operations. The primary
operation of the ALU is to take zero or more operands and perform the
function called for in the instruction. In addition to the ALU, the CPU
consists of a set of registers to store operands and intermediate results of
computations and to maintain information used by the CPU to determine
the state of its computations. For example, there are registers for the status
of the ALU's operation, for keeping count of the instruction to be per-
formed next, to keep data flowing in from memory or out to memory, to
maintain the instruction being executed, and for the location of operands
being operated on by the CPU. Each of these registers has a unique func-
tion within the CPU, and each is necessary for various classes of computer
architectures. A typical minimal architecture for a CPU and its registers is
shown in Figure 1.3 and consists of a primary memory connected to the
CPU via buses. There are registers in the CPU for holding instructions,
instruction operands, and results of operations; a program location counter,
containing either the location in memory for instructions or operands,
depending on the decoding of instructions; and a program counter contain-
ing the location of the next instruction to perform.
The CPU also contains the control unit. The control unit uses the status
registers and instructions in the instruction register to determine what func-
tions the CPU must perform on the registers, ALU, and data paths that
make up the CPU. The basic operation of the CPU follows a simple loop,
I Chapter I
6 I. I Evolutionof computer systemsarchitectures
L
Y
Figure 1.3
Typical CP U MAR
architecture.
.I"1 Memory I~ MDR ALU+ I
Control' [~
IR I
Data
reg
/
Operands and Results CPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
called the instruction execution cycle (Figure 1.4). There are six basic func-
tions performed in the instruction loop: instruction fetch, instruction
decode, operand effective address calculation, operand fetch, operation exe-
cution, and next address calculation. This execution sequence represents the
basic functions found in all computer systems. Variations in the number of
steps are found based on the type and length of the instruction.
There are numerous ideas about how to organize computer systems around
the instruction set. One form, which has come of age with the new power-
fill workstations, is the reduced instruction set computer (RISC), where
each instruction is simple, but highly optimized. On the far spectrum of
architectures is the very long word instruction architecture, where each
Memory-addressing schemes
There are also numerous ways in which to determine the address of an oper-
and from an instruction. Each address computation method has its benefits
in terms of instruction design flexibility. There are six major types of
addressing computation schemes found in computers: immediate, direct,
index, base, indirect, and two-operand. We will examine these further in
Chapter 2.
I.I.3 M e m o r y architectures
Figure 1.5
CP U memory
access.
Memory
Array
OPU
I Chapter I
8 I. I Evolutionof computersystemsarchitectures
StorageDensity
IL
Disk
AccessSpeed (~ Tape
I.I.6 N e t w o r k architectures
Figure 1.7
Basic computer
architecture.
I/0 CPU Memory
IPrinterI
~ I 'ter I
I Chapter I
I0 1.2 Evolutionof database systems
Figure 1.9
Common bus CPU m Memory I/0
architecture.
l l
y
I/0 Bus
Figure 1.10
Dual bus
architecture.
CPU Memory I/0
Memory
Bus
1.2 E v o l u t i o n of d a t a b a s e systems
Database systems have been with us since the 1960s as research vehicles
(first-generation products wrapped around the hierarchical and network
data models) and since the mid 1980s as fully functional products using the
relational data model. Since these early beginnings, database systems have
evolved from simple repositories for persistent information to very powerful
tools for information management and use.
Database systems have been of interest to the computer systems
performance analyst and to computer systems applications developers since
the earliest days of commercial computers. Early computer systems lacked
extensive on-line data storage (primary memory as well as secondary disk
storage), forcing systems architects and developers to rely heavily on exter-
nally archived information (typically stored in tape drives). Initial data stor-
age repositories were constructed using simple direct addressing schemes
that linked specific storage to a specific device and specific location on that
device. For example, to extract a piece of information an application needed
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160 grains.
PLATE III.
Large Pattern Cent. Not Issued. Bar Cent. Very Rare.
Fugio. “Mind Your Business.” First. Inimica Tyrannis Americana. Fugio.
“Mind Your Business.” Second.
See description.
PLATE IV.
Half Cent. 1836. Confederate C. S. A. Half Dollar. Half Cent. 1840.
Half Cent. 1845. “Jefferson Head” Cent. Half Cent. 1846.
See description.
Maryland Penny.
The Maryland Penny. One Type. One Variety. Unique.
Obverse: Similar to that of the sixpence.
Reverse: A Ducal Coronet, upon which are erected two masts,
each bearing a flying pennant. Legend: “denarivm terre-mariæ.”
Copper; size, 13.
The only specimen of this piece extant was imported into America
from England, at a cost of £75, and was sold for $370 with the
collection of J. J. Mickley, Esq., of Philadelphia.
PLATE V.
Maryland Penny. Half Cent. 1847. Rosa Americana Half Penny. 1722.
Liber Natus Libernatum Defendo. First. Granby or Higley Token. 1737.
Liber Natus Libernatum Defendo. Second.
See description.
PLATE VI.
Washington Cent. 1783. Washington Liverpool Half Penny. 1793. “Naked
Bust.” Washington Cent. 1792.
Non Dependens Status. Half Cent. 1842. Pattern Cent. 1792.
See description.
PLATE VII.
George Clinton Copper. 1787. Kentucky Token. Immunis Columbia. 1787.
Massachusetts Pine Tree Shilling. 1652. Chain Cent. 1793. Myddelton
Token.
See description.
PLATE VIII.
Greek Egyptian Coin. Ptolemæus Soter. 285-300 B. C. Roman Coin.
Faustina, Daughter of Antoninus Pius, Wife of Marcus Aurelius. Died, 175
A. D. Macedonian Silver Coin. Alexander the Great. 300 Years B. C.
Silver Shekel of Judea. Simon Maccabees. 145 B. C. Persian Silver Coin.
Vologeses III. 148-190 A. D. Judean Copper Coin. Simon Maccabees. 145 B.
C.
See description.
Chain Cents.
These have a bust with flowing hair, looking right, with the date
below and word “liberty” above it; on the reverse side, in the
centre, is “one cent,” with “⅟₁₀₀” below it, enclosed in an endless
chain of fifteen links, typifying the number of States then in the
Union. The legend is “united states of america” in all excepting
one die, which reads “united states of ameri,” the engraver
evidently not having room to complete the word.
PLATE X.
Greek Egyptian Coin. Ptolemy. Widow’s Mite. Copper Coin. Roman Bronze
Coin. Trajan Augustus. 98-117 A. D.
Antiochus Epiphanes. Counterfeit Judean Shekel. Dating about the Time
of Christ. Macedonian Coin. Philip III. 317-324 B. C.
See description.
Cent, 1799.
The liberty cap is omitted, as is the lettering on the edge, not to
reappear on the American cent. Liberty Cap Cents are very rare.
In the year 1798 a slight change was made in the obverse of the
cent, giving some of the curls a different termination from those of
1796, 1797, and the early part of 1798. The latter device was
continued each year, until and including 1807. The reverse remained
unchanged during the same time, excepting some slight variations,
probably unintentional, if not positive mistakes. For instance, in 1797
and 1802 we find some without stems to the wreaths, and in one
case only one stem. In 1801 and 1802 some have ⅟₀₀₀ instead of
the fraction ⅟₁₀₀. In addition to this error, a variety of the cent of
1802 has “Iinited,” instead of “United.” In 1796 we have in one
instance “Liherty,” instead of “Liberty.”
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