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S. Jayanthy · M. C. Bhuvaneswari

Test Generation
of Crosstalk
Delay Faults in
VLSI Circuits
Test Generation of Crosstalk Delay Faults in VLSI
Circuits
S. Jayanthy M. C. Bhuvaneswari
•

Test Generation of Crosstalk

Delay Faults in VLSI Circuits

123
S. Jayanthy M. C. Bhuvaneswari
Department of Electronics and Department of Electrical
Communication Engineering and Electronics Engineering
Sri Ramakrishna Engineering College PSG College of Technology
Coimbatore, Tamil Nadu, India Coimbatore, Tamil Nadu, India

ISBN 978-981-13-2492-5 ISBN 978-981-13-2493-2 (eBook)

https://doi.org/10.1007/978-981-13-2493-2

Library of Congress Control Number: 2018954035

© Springer Science+Business Media Singapore 2019

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained herein or
for any errors or omissions that may have been made. The publisher remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.

This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd.
The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721,
Singapore
Preface

This book describes the various test generation algorithms for testing crosstalk
delay faults in VLSI circuits.
Testing is an essential part of any integrated circuit manufacturing system. The
problem of test generation is NP-complete problems, and it is becoming more and
more difficult as system-on-chip designs have approached the deep submicron era.
In addition to the propagation delay, deep submicron technology (DSM) effects will
create severe signal integrity problems. Timing-related defects and signal integrity
problems are introduced by imperfect manufacturing process, process variations,
electromigration, voltage drop in power lines, crosstalk noise, and crosstalk delay
which will cause the chip to fail. Crosstalk delay and crosstalk noise are caused due
to the increased coupling capacitance. As more number of transistors are integrated
on a chip, there is an increase in their aspect ratio and a decrease in the spacing
between the interconnects, and thus, the interconnect coupling capacitances become
larger. This increases the ratio between the coupling capacitance and the total
capacitance leading to an increase in capacitive coupling noise. Crosstalk will
become the major contributor to the interconnect delay in the near future. It is
impossible to estimate the timing faults due to crosstalk delay in the design stage
due to process variations and manufacturing defects. Hence, there is a need for
automatic test pattern generation (ATPG) algorithms that can generate test vectors
for testing the chips for crosstalk delay faults to ensure quality.
Crosstalk delay fault is induced in the circuit if the victim and aggressor lines
have simultaneous transitions. Crosstalk is most frequently observed for long nets
which may have multiple fanouts. Thus, a long net is capacitively coupled with
multiple aggressors. Hence, test pattern generation algorithms need to generate test
vectors to activate multiple aggressors coupled to a victim.
This book provides an introduction to the various crosstalk effects and describes
the deterministic and simulation-based methods for testing crosstalk delay faults.

v
vi Preface

Organization of the Book

The content of this book is divided into ten chapters. The first three chapters focus
on the existing crosstalk delay models, test generation algorithms for delay faults,
and crosstalk delay faults. The remaining chapters deal with the deterministic
algorithms and simulation-based algorithms applied for testing crosstalk delay
faults. The experimental results for the algorithms and analysis are given.
Chapter 1 focuses on the current scenario in VLSI testing and provides an insight
into the crosstalk effects. The existing crosstalk delay fault models are discussed.
Chapter 2 discusses the delay fault testing in VLSI circuits. It describes various
delay fault models and test application schemes for the delay fault testing. It gives a
survey of existing test generation and simulation-based algorithms for testing the
delay faults in combinational and sequential circuits.
Chapter 3 discusses the existing test generation techniques for crosstalk delay
faults. Both deterministic and simulation-based techniques are discussed.
Chapter 4 describes the static timing analysis for the identification of crosstalk
delay faults. It deals with efficient ATPG for crosstalk delay faults based on the
modified PODEM and modified FAN. Experimental results for ISCAS’85 combi-
national circuits, enhanced scan version of ISCAS’89 sequential circuits, and ITC’
99 benchmark circuits are presented.
Chapter 5 focuses on the application of genetic algorithms for crosstalk delay fault
testing. Test results for four crossover operators, namely one-point, two-point, uniform,
and weight-based crossover operators, are reported for ISCAS’85 combinational cir-
cuits, several enhanced scan version of ISCAS’89 sequential circuits, and ITC’99
benchmark circuits. The results obtained are compared with the previous works.
Chapter 6 describes a crosstalk delay fault test generation methodology using
single-objective particle swarm optimization (PSO). The experimental results are
presented and discussed.
Chapter 7 deals with multiobjective genetic algorithms WSGA, NSGA-II, and
NSGA-II with redundancy for test generation for crosstalk delay faults. The
experimental results are presented and discussed.
Chapter 8 gives an introduction to fuzzy delay model. The fuzzy delay model-based
simulation algorithm for asynchronous circuits is presented. The simulation-based test
generation results for random patterns are presented for SIS benchmark circuits.
Chapter 9 explains a simulation-based method for test generation for crosstalk
delay faults in asynchronous sequential circuits. GA-based ATPG, WSGA-based
ATPG, and NSGA-II-based ATPG for crosstalk delay faults in asynchronous
sequential circuits are presented. Experimental results for SIS benchmark circuits
are reported.
Chapter 10 deals with the overall summary of the research discussed in each
of the chapters and the future research prospects of crosstalk delay fault testing.

Coimbatore, India S. Jayanthy

M. C. Bhuvaneswari
Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 1
1.2 VLSI Design Flow . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 2
1.3 VLSI Testing . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 4
1.4 Test Challenges for Deep Submicron Technologies . . . . . . . . . . 5
1.5 Crosstalk Effects . . . . . . . . . . . . . . . ........... . . . . . . . . . 8
1.6 Crosstalk Fault Models . . . . . . . . . . ........... . . . . . . . . . 10
1.7 Conclusion . . . . . . . . . . . . . . . . . . . ........... . . . . . . . . . 13
References . . . . . . . . . . . . . . . . . . . . . . . . ........... . . . . . . . . . 13
2 Delay Fault Testing of VLSI Circuits . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Delay Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Gate Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.3 Line Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.4 Path Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.5 Segment Delay Fault Model . . . . . . . . . . . . . . . . . . . . . 20
2.3 Test Application Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 Standard Scan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 For Non-Scan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Test Generation Methods for Path Delay Fault Model . . . . . . . . 25
2.4.1 Path Delay Fault Simulation . . . . . . . . ...... . . . . . . . 25
2.4.2 Test Generation for Path Delay Faults . ...... . . . . . . . 29
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . 34
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . 34
3 Test Generation Algorithms for Crosstalk Faults . . . . . . . . . . . . . . 37
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Test Generation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

vii
viii Contents

3.3 Test Generation for Crosstalk Pulses . . . . . . . . . . . . . . . . . . . . 42

3.3.1 Deterministic Algorithms . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.2 Simulation-Based TG . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 Test Generation Techniques for Crosstalk Delay Faults . . . . . . . 46
3.4.1 Deterministic Algorithms . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.2 Simulation-Based Test Generation . . . . . . . . . . . . . . . . . 50
3.5 Delay Testing of Asynchronous Sequential Circuits . . . . . . . . . 51
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 An Automatic Test Generation Method for Crosstalk Delay
Faults Using Modified FAN Algorithm . . . . . . . . . . . . . . . . . . . . . . 57
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.1 Identification of Target Crosstalk Faults . . . . . . . . . . . . 58
4.3 Seven-Valued Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Procedure for Modified PODEM-Based Test Generation . . . . . . 62
4.5 Procedure for Modified FAN-Based Test Generation . . . . . . . . . 65
4.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5 ATPG for Crosstalk Delay Faults using Single-Objective
Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2 Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3 Test Generation Using GA . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 Chromosome Encoding . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2 Fitness Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 Crossover Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4 Crosstalk Delay Fault Simulator . . . . . . . . . . . . . . . . . . . . . . . 85
5.5 GA-Based Crosstalk Delay Test Generation Algorithm . . . . . . . 86
5.5.1 Phase I: Pseudorandom Generation of Initial Test
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.5.2 Phase II: GA-Based Test Generation . . . . . . . . . . . . . . . 87
5.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6 ATPG for Crosstalk Delay Faults Using Particle Swarm
Optimization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Particle Swarm Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3 PSO Algorithm-Based Test Generation Algorithm . . . . . . . . . . 102
Contents ix

6.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7 ATPG for Crosstalk Delay Faults Using Multi-objective
Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.2 Weighted Sum-Based ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3 Optimization Using NSGA-II . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.3.1 Elitism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.3.2 Non-dominated Sorting . . . . . . . . . . . . . . . . . . . . . . . . 113
7.3.3 Crowding Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.4 NSGA-II-Based ATPG with Redundancy . . . . . . . . . . . . . . . . . 115
7.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8 Simulation of Asynchronous Sequential Circuits Using Fuzzy
Delay Model for Crosstalk Delay Faults . . . . . . . . . . . . . . . . . . . . . 125
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2 Races, Oscillations, and Non-confluence . . . . . . . . . . . . . . . . . 126
8.3 Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.3.1 Types of Delay Models . . . . . . . . . . . . . . . . . . . . . . . . 127
8.4 Fuzzy Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.4.1 Fuzzy Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.4.2 Logic Gate Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.4.3 Representation of Fuzzy Delay . . . . . . . . . . . . . . . . . . . 131
8.5 Discrete Event-Driven Logic Simulation Based on Fuzzy
Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.5.1 Component State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.5.2 State Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.5.3 Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.5.4 Processing of Events . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.6 Crosstalk Delay Fault Simulation Algorithm . . . . . . . . . . . . . . . 135
8.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9 Simulation Based Test Generation for Crosstalk Delay Faults
in Asynchronous Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . 141
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.2 Feedback Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.3 Crosstalk Delay Fault Simulator for Asynchronous
Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
x Contents

9.4 GA-Based ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.4.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.5 WSGA- and NSGA-II-Based ATPG . . . . . . . . . . . . . . . . . . . . 145
9.5.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10 Summary and Suggestions for Future Research . . . . . . . . . . . . . . . 151
10.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.2 Suggestions for Future Research . . . . . . . . . . . . . . . . . . . . . . . 155
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
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About the Authors

Dr. S. Jayanthy is Professor in the Department of Electronics and Communication

Engineering, Sri Ramakrishna Engineering College, Coimbatore, India. She
received her master’s and Ph.D. from PSG College of Technology, Coimbatore,
and Anna University, Chennai, respectively. Her research interests are in VLSI
design and testing, genetic algorithms, and embedded systems. With more than
20 years of teaching experience, she has published 2 chapters and more than
40 research papers in journals and national and international conferences and has
organized a number of workshops and national conferences in the areas of VLSI,
embedded systems, and IoT. She is a life member of Indian Society for Technical
Education and Institution of Electronics and Telecommunication Engineers.
Dr. M. C. Bhuvaneswari is Associate Professor in the Department of Electrical
and Electronics Engineering, PSG College of Technology, Coimbatore, India. She
received her B.E. in electronics and communications engineering from Madras
University and her M.E. and Ph.D. from Bharathiar University. Her research
interests include applied electronics, VLSI design and testing, genetic algorithms,
digital system design, and microprocessors. She has published a book on VLSI and
embedded systems (2015) and authored more than 90 research papers in journals
and national and international conferences. She is a life member of Indian Society
for Technical Education, Institute of Engineers (India), Computer Society of India,
and Systems Society of India. She was honored with Dakshinamoorthy Award for
Teaching Excellence instituted by PSG College of Technology in the year 2010.

xi
Chapter 1
Introduction

1.1 Introduction

Rapid advances in integrated circuit (IC) technology have made it possible to fabri-
cate digital circuits with large number of devices on a single chip. The advantages of
integrated circuits are reduced system cost, better performance, and reliability. These
advantages would be lost unless integrated circuit devices can be economically tested.
Testing is one of the important fields, which validates the functionality of any man-
ufacturing process. The testing process detects the physical defects produced during
fabrication. The problem of test generation belongs to a class of NP-complete prob-
lems, and it is becoming more and more difficult as the complexity of IC increases.
Scaling of process technologies could be limited if testability issues are not
addressed adequately. This is because defect sizes have not reduced in proportion
with shrinking geometries. The major factors that affect the functionality in deep
submicron technologies (DSM) are process variations, manufacturing defects, and
noise. Process variations can have a major affect on chip’s failure to meet the speci-
fied performance. Delay defects which are caused by interconnect defects and noise
sources such as crosstalk, power supply noise, and substrate noise will result in chips
failing to meet the timing specifications. In order to guarantee optimal performance
of DSM chips, their functional correctness as well as timing behavior needs to be
tested. Hence, current test and verification techniques need to be improved. More
detailed fault models are required to model the behavior of faulty deep submicron
chips. Therefore, efficient test techniques are needed to detect such defects and elim-
inate them before products are shipped (Datta et al. 2009).

© Springer Science+Business Media Singapore 2019 1

S. Jayanthy and M. C. Bhuvaneswari, Test Generation of Crosstalk Delay
Faults in VLSI Circuits, https://doi.org/10.1007/978-981-13-2493-2_1
2 1 Introduction

1.2 VLSI Design Flow

VLSI is a field which involves packing of millions of components on the same chip.
Due to the significant improvements in the IC manufacturing, the capability of IC has
increased in terms of computational power, utilization of available area, and yield.
The design of such ICs has become a complicated and time-consuming process.
Therefore, there is a necessity for the development of powerful design tools and
software systems that help a VLSI design engineer to produce a fault-free IC chip.
The various steps in IC design and manufacturing are shown in Fig. 1.1. A
design specification is formulated based on a customer or project need. Specifications
describe the functionality, interface, and overall architecture of the IC to be designed.
This idea is casted into the model which captures the function that the circuit will
perform. Design engineers create a behavioral-, logical-, or circuit-level model of the
specification. Design typically starts at very high levels of abstraction using some
high-level hardware description language (HDL) (Bhuvaneswari and Sivanandam
2001). Design verification is done to ensure that the design will perform the required
functions when manufactured.
A logical-level implementation is synthesized from the HDL specifications which
should be verified to ensure that the final design meets timing, area, and power speci-
fications. When design error is found, modifications are done and design verification
is repeated. As a result, design verification is considered as a form of testing. The
logical-level description is transformed into physical-level description to obtain the
placement and interconnection of the transistors in the VLSI device. This physical-
level description is verified for timing and specified operating frequency specifica-
tions, and then, the design is fabricated. At the same time, test engineers develop
a test procedure based on the design specification and fault models associated with
the fabrication technology. The unavoidable statistical flaws in the materials and
masks used to fabricate ICs result in defects during the fabrication process. Hence,
the ICs fabricated on the wafer are tested for fabrication faults to determine which
devices are defective. The chips that pass wafer-level test are extracted and packaged.
The packaged devices are further tested for any damages in the packaging process.
Finally, devices pass through final quality test before going to market. This includes
measurement of input/output timing specifications, voltage, and current (Wang et al.
2006).
Better electronic design automation (EDA) tools, advanced technology IC man-
ufacturing, and design flow methodology are required for successful delivery of
finished products. The EDA tools and design flow methodology are directly affected
when there is a change in IC technology. The deep submicron IC manufacturing tech-
nology has had a direct influence on both the EDA tools and design flow methodology.
As design moves from the architectural level to the physical representation or fabri-
cation, the complexity of the design increases. There could be several iterations of
each phase during the IC development to ensure quality and performance. During the
various iterations, several computer-aided design (CAD) tools assist in translating
the design into an IC. The CAD techniques have reached good level of maturity
1.2 VLSI Design Flow 3

Fig. 1.1 Typical design flow

of IC Design

Architectural design

Functional verification
and testing

Logical design

Logical verification and

testing

Physical design

Physical layout
verification

Fabrication

Chip

in many areas. But as technology moves into nanometer age, in order to keep up
with the Moore’s law, many new technologies and circuit design techniques must
be devised and adopted. This may give rise to severe test challenges that must be
solved concurrently. When the feature size becomes less than 100 nm, a small defect
would result in a faulty transistor or an interconnection. But this one faulty tran-
sistor or interconnection is enough for improper functioning of the entire chip with
respect to its operation or timing. But these small defects during the manufacturing
process cannot be avoided, and it is required to test all the products whether it is a
VLSI device or a system consisting of many VLSI devices. During manufacturing
process, testing is done at various stages. Testing electronic devices includes test-
ing at the various manufacturing stages that are during IC fabrication, during PCB
4 1 Introduction

layout, during system integration, and during system operation. Testing is used to
find the fault-free devices during these stages. The source of defects is analyzed at
the various stages of manufacturing to improve production yield. Periodic testing of
systems is also performed to ensure that system operates as per requirements, and as
and when faults are detected, corrective action is initiated. VLSI testing is important
in all stages viz design, production, testing, manufacturing, and at field.

1.3 VLSI Testing

Tests may fall into two main categories, the functionality test and manufacturing test.
The functionality tests are usually done early in the design cycle to verify whether
the IC performs its intended function. Manufacturing test involves development of
test patterns to ensure ICs operate correctly before being delivered to customers. This
is an important stage of IC development as it affects the quality of the product. In
any manufacturing process, fabrication defects are invariably introduced. Common
defects are shorts, opens, improper doping profiles, mask alignment errors, and poor
encapsulation (Abramovici et al. 1990). The testing process detects the physical
defects produced during fabrication of an integrated circuit chip. Testing of a die/chip
can occur at the wafer level, packed chip level, board level, system level, or in the
field. The cost of identifying a faulty component is lowest before it is packed (Hurst
1998). This cost increases as component becomes a part of a larger system. Due to the
complexity of the IC manufacturing process, a number of defects might occur during
fabrication and hence no process can guarantee 100% yield. If these test issues are
not solved, in future the cost of testing a transistor might become more than the cost
of designing the transistor. Therefore, testing is an important aspect of any integrated
circuit manufacturing system.
Testing is a process which validates the functionality of any manufacturing pro-
cess. Testing a product after manufacturing is essential to reduce the risk of shipping
a defective product and is a process where circuit inputs are exercised using certain
patterns and the resulting response is compared to the golden response to eliminate
the defective parts. Automatic test generation refers to the test generation algorithms
that, given a model of the system, can generate tests for it. Covering all the faults
would be very difficult and would require an inordinate number of test vectors. There-
fore, automatic test generation tools operate on an abstract representation of defects
referred as faults and model a subset of potential faults. The faults in digital circuit
are referred as logic or parametric faults. A logic fault causes the logic function of
the circuit, on an output signal to be changed to some incorrect function. Paramet-
ric faults are the faults, which alter the magnitude of the circuit parameters causing
changes in speed of operation or the levels of voltages and currents.
The effects of manufacturing defects are represented at the logic level using a
fault model. Fault models can describe the faults at different abstraction levels. The
common abstraction level is the gate level. Most fault models assume that the circuit
contains only a single fault, as the number of potential multiple fault combinations
1.3 VLSI Testing 5

is so large that test generation becomes infeasible. The widely used gate-level fault
model for digital circuits is the single stuck-at fault model. This model assumes that
any physical defect in a digital circuit results in a node in the circuit being fixed either
at logic 0 or at logic 1 and appropriately called stuck-at-0 and stuck-at-1, respectively.
It can be considered as a direct connection between a node and power (stuck-at-1)
or ground (stuck-at-0). These faults occur most frequently in complementary metal
oxide semiconductor (CMOS) process technology due to thin oxide shorts, that is, in
a n-transistor gate may be shorted to V ss and in the p-transistor gate may be shorted
to V dd or metal to metal shorts. The stuck-at fault model has several advantages.
The advantages include simplicity, logical behavior, tractability, and measurability.
In multiple stuck-at fault model, a circuit with m signal can have (3m − 1) possible
faults since each signal can be s-a-0, s-a-1, or fault free. This is a very large number
even for relatively small circuits. For simplicity, it is assumed that only one stuck-at
fault will be present at any given time. In the single stuck-at (SSA) fault model, a
circuit with m signals can have at most 2m faults. The number of faults to be explicitly
analyzed can be further reduced by fault collapsing techniques. Fault collapsing can
be done by two methods: fault equivalence and fault dominance.
Fault-free operation of a logic circuit requires not only performing the logic func-
tion correctly but also propagating the correct logic signals along paths within a
specified time limit. A delay fault causes excessive delay along a path such that the
total propagation delay falls outside the specified limit. Delay faults have become
more prevalent with decreasing feature sizes.

1.4 Test Challenges for Deep Submicron Technologies

The advent of nanometer technology has paved way for a significant increase in the
level of integration and performance of VLSI chips. As more number of transistors
is fabricated on a single chip, the cost per transistor reduces. However, testability
becomes a significant factor for achieving acceptable reliability levels for modern
VLSI chips. This is because the defect size has not scaled down in proportion to
shrinking geometries. Further increase in wiring levels and wire delay demands new
fault models. Moreover, signal integrity problems such as crosstalk noise, excessive
voltage drop, and substrate and thermal noise cause devices to violate performance
specifications. Process variations also can have a considerable influence on a chip’s
failure to meet specified performance. The noise sources and process variations cause
timing-related defects that change the timing of the circuit. The advent of system-
on-chip (SOC) architectures, high-frequency circuits, and microelectromechanical
(MEMSs) circuits and programmable gate arrays further heightens these issues.
As semiconductor process technologies size down toward nanometer era, feature
size continues to shrink. Although lesser transistor size could result in lesser circuit
delay, a smaller feature size for interconnects does not reduce the signal propaga-
tion delay. This is because the cross section becomes smaller due to reduced feature
size and hence increases the line’s resistance. To reduce the resistance, the aspect
6 1 Introduction

ratio is made larger than one while maintaining high horizontal interconnect density,
but this increases the coupling capacitance. Further, the spacing between intercon-
necting lines is smaller. Hence, the effective capacitance increases. This along with
the increase in line resistance increases the RC time constant and hence the circuit
delay. Thus, the signal propagation delay in interconnects has become a major fac-
tor in determining the delay of a circuit. To solve these problems, low-resistivity
lines and low-permittivity dielectric materials can be used to reduce capacitance.
Another solution is reverse scaling of the upper levels of interconnects, presenting a
greater cross section. But these two solutions increase the inductive coupling, which
depends on the return current path, and do not scale proportionally with capacitance
and resistance. The upper levels which form the global interconnects are little fur-
ther from substrate and hence have higher characteristic impedance. This is called
as signal integrity problem which will have a significant adverse effect on the proper
functioning and performance of VLSI systems.
Simultaneous switching of digital gates produces spikes which cause simultaneous
switching noise, which is known as power supply noise, or ground/power bounce.
The supply voltage pin of the IC package produces a series resistance and inductance
in the path from the external power supply to the on-chip power supply. Considering
a single gate, the voltage at any instant at the power supply due to these effects will
be supply voltage subtracted by the voltage drop across the resistance and inductance
in the on-chip supply voltage. The return path of current passes through the ground
pin of the package thus closing the loop and generating a positive spike at the on-
chip ground pin. The overall effect is a transient reduction in the on-chip power
supply voltage. The time derivative of the current is proportional to the input rise or
fall time and the transistors’ maximum saturation current. When a number of gates
switch simultaneously, the combination of individual switching currents increases
the amount of SSN. To improve system performance and maximize clock frequency,
path delay distribution of different propagation paths is made as narrow as possible.
This increases simultaneity because nearly all paths have similar delays, and the
gates along those paths switch almost simultaneously and increase SSN. For deep
submicron designs with frequency in the gigahertz range and high circuit density, the
power supply voltage drop caused by instantaneous change in current is comparable
to IR drop. Therefore, the on-chip power supply is not the same across the chip. This
has caused power integrity problem which can affect reliability and performance of
VLSI circuits. This power supply noise can reduce the actual output voltage of a
device, which in turn can increase the cell and interconnection propagation delay,
causes false switching of logic gates, and affects the performance of the analog and
RF sections of mixed signal integrated circuits (Wang et al. 2006).
Substrate noise has become an important problem in mixed digital/analog circuits.
Noise sources include switching devices, substrate contacts, and switching intercon-
nects. Receiving device is affected through parasitic capacitances and body effect.
Regarding the propagation path, CMOS technology uses two different types of sub-
strates. Digital technologies use highly conductive substrates with a thin epitaxial
layer at the top. In these substrates, noise penetrates the upper layer and propagates on
top of the conductive layer. High-frequency analog circuits use substrates that have
1.4 Test Challenges for Deep Submicron Technologies 7

a uniform high resistivity. Here, noise current densities are higher near the surface,
decreasing more deeply inside the low-conductive substrate. Results in mixed signal
circuits show that first type of substrate propagates noise three times as substrates
with uniform resistivity. Special packaging and grounding techniques can reduce the
substrate noise. To reduce substrate noise, sensitive circuitry is designed so that it is
immune to noise. The amount of noise generated and injected into the substrate is
reduced, and the noise is prevented from reaching the critical parts by using either
inert barriers or noise sinking.
With significant advances in IC technology, precise control of the silicon process
has become difficult. There are two types of process variations: variations within
the same fabrication plant and between fabrication plants. The variations between
chips manufactured in the same fabrication plant include line-to-line, wafer-to-wafer,
inter-die, and intra-die variations. Process variations which influence the entire chip
or functional block are inter-die variations. These are caused due to process gradient
effects over the wafer. Process variations which are not uniform over the entire die
are called intra-die variations. Because of these effects, channel length of the tran-
sistor has become difficult to control, variation in thickness of interconnects, gate
length variation, random placement of dopant in channel. These variations result in
delays of wires and gates within a chip. Different fabrication plants use different cell
libraries, and hence, the resulting synthesized circuitry causes variations between
chips. However, latter is rarely used and hence does not produce a significant effect.
This is a process variation problem as design approaches submicrons. These varia-
tions cause distributed delay faults in the chip, which in turn give rise to small delay
faults on multiple gates in a given path to accumulate and result in the path failing
to meet performance specifications, which may affect the yield and performance of
devices.
Productivity gap results due to this timing inaccuracy, as both EDA tools and
design flow methodology break as they cannot change rapidly with the changes in IC
technology in deep submicron designs. Hence, new fault models and test methods
are to be developed concurrently with the development of new nanotechnologies and
circuit designs and placed in the various stages of design to reduce the productivity
gap. With increasing system complexity, current test and verification techniques need
to be improved. Fault models like stuck-at-fault model, which correctly modeled
the behavior of defective chips earlier, are not effective to adequately represent the
majority of IC defects and new failure mechanisms in deep submicron technologies.
Existing design for test, fault simulation, and ATPG tools must move to more realistic
fault types to meet increased quality expectations. Before the chip is fabricated on
silicon, there is a need to check for functional design errors, timing errors, and
design rule violations. Only a model-based design is verified and detailed modeling
of circuits increases computational cost. Hence, a structured technique for testing
becomes necessary to locate and rectify any design error in first silicon. Testing of
a chip requires analysis of its both internal behavior and external behavior under
known stimuli. The analysis is repeated and the responses obtained are compared
with a set of expected responses to locate design errors. Faults in design are located
and rectified by repeating the design cycle before the final chip is manufactured.
8 1 Introduction

When feature sizes are reduced, the observability of chips for timing violations
becomes difficult. For optimum yield, the chips should have both functional and
timing correctness. With decrease in feature sizes, delay faults in chips have become
a significant problem.
The Semiconductor Industry Association (SIA) has published an International
Technology Roadmap for Semiconductors (ITRS) which includes the updates on
test and test equipment trends for nanometer designs. The long-time challenges for
nanometer designs with feature size less than or equal to 45 nm include the full
spectrum of test technology trends which include new automatic test equipment
(ATE) interfaces, test methodologies, improved defect analysis, failure analysis, and
device technologies (Wang et al. 2006).

1.5 Crosstalk Effects

Noise is one of the most significant factors that affect the deep submicron VLSI
designs. Among the various noise sources, problems related to crosstalk noise
between circuit interconnects have become a dominant source of noise in deep submi-
cron circuits (Gal 1995). High-speed digital circuits to a great extent use the dynamic
logic family. Dynamic circuits with their two phases of operations are more suscep-
tible to crosstalk noise compared to the static logic (Heydari and Pedram 2001).
Line capacitance and load capacitance dominate circuit behavior for submicron pro-
cess. For deep submicron technologies, cross-coupling capacitance dominates due
to decrease in spacing between conductors, the increase in height to width ratio of
each conductor, the raise in length of adjoining conductors, and increase in metal
layers. The coupling capacitance becomes a significant contributor to signal integrity
problem Bhuvaneswari and Jayanthy (2015).
Coupling causes insertion of noise into near lines from active lines. This method
of noise coupling is called crosstalk. With the intensive scaling in process technology
and increase in switching speed, the problem of modeling gate delays becomes fur-
ther difficult. In deep submicron VLSI designs, the part of delay contributed by gates
reduces while interconnect delay becomes dominant. This is due to the fact that the
scaling of interconnect lengths is not in proportion to the shrinking size of transistors
that make up the gates. Further as operating frequencies increase, on-chip induc-
tance and cross-coupling capacitance between the interconnect lines also increase.
Inductances in a wire are of low magnitude value. It becomes significant only at
very high frequencies in global lines such as ground and power supply lines and is
important only in power circuits. Hence, the cross-coupling capacitance or crosstalk
noise effects are considered to have a predominant effect in digital circuits that may
result in improper functioning of a chip (Aragones et al. 2002). Crosstalk noise may
cause unwanted effects including excessive overshoot, undershoot, glitches, addi-
tional signal delay, and even a decrease in signal delay. These effects can lead to
possible circuit malfunction and increased power dissipation.
1.5 Crosstalk Effects 9

Fig. 1.2 a Positive pulse, b (a) (b)

negative pulse
Static 0 Static 1

Victim-line Victim-line
Aggress Aggressor-
or-line line

Rising Falling
transition transition

There are two main types of crosstalk effects: crosstalk-induced pulses and
crosstalk-induced delay. Given a pair of nodes with capacitive crosstalk interac-
tion, there is always one of them that act as affecting node or aggressor and the other
as affected or victim node. A crosstalk glitch is a pulse that is induced by coupling
effects among interconnect lines. The amplitude and the width of the glitch depend
on relative switching time of the aggressors, the amount of coupling capacitance,
line-to-ground capacitance, and the relative transition times of the aggressors. When
aggressor nodes are applied a transition signal and the stable signals applied to vic-
tim node, the stable signal may experience coupling noise due to transition in the
aggressor nodes.
In Fig. 1.2, the victim line remains in a static 0 state and one aggressor line has
a rising transition. The aggressor creates a positive pulse on the victim line, which
depending on its amplitude and width will have an effect on the circuit performance
(Moll and Rubio 1992). In the second case, victim line remains in a static 1 state and
one aggressor line has a negative transition, which creates a negative pulse on the
victim line.
Crosstalk delay is a signal delay induced by the identical coupling effects, that
is, simultaneous transitions among interconnect lines. Crosstalk causes a delay in
addition to normal gate delay and interconnect delay. Hence, it is difficult to estimate
the correct circuit delay which may lead to severe signal delay problems (Wang et al.
2006). These unexpected changes in signal propagation delays cause delay faults
which cause the delay of paths in a chip to be larger than expected resulting in the
output of a chip to deviate from the expected behavior, in spite of the chip being
functionally correct.
As shown in Fig. 1.3, the victim and aggressor have transitions in the opposite
direction, and hence, signal delay increases and speed of circuit decreases. In the
second case, if the transitions are in the same direction, signal delay decreases thus
increasing the speed of the circuit. These changes in signal propagation delays can
cause faulty behaviors of digital circuits.
When designing fault analysis tools, these delays have to be taken into consid-
eration. Several physical designs (Vittal and Marek-Sadowska 1997; Elgamel et al.
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10 1 Introduction

Fig. 1.3 a Crosstalk (a) (b)

slowdown, b crosstalk
speedup

Victim- Victim-
line line

Aggresso Aggresso
r-line r-line

2005; Hunagund and Kalpana 2010) and analysis tools (Agarwal et al. 2006; Kaushik
and Sarkar 2008; Palit et al. 2009; Shahin and Pedram 2010) are being developed
to aid in designs that minimize crosstalk. But during manufacturing, process varia-
tions and manufacturing defects may aggravate crosstalk effects (Chen et al. 1998).
Hence, it is necessary to develop new crosstalk fault models and testing techniques
for manufacturing defects that produce crosstalk effects.

1.6 Crosstalk Fault Models

There are three important delay fault models at logic level: transition fault model,
gate delay fault model, and path delay fault model. Transition and gate delay models
represent delay defects lumped at gates, and path delay model represents defects that
are distributed over several gates.
Some researchers Chen et al. (1998, 1999, 2002) Sinha et al. (2003, 2008) have
used transition fault model, whereas the others Li et al. (2003, 2005, 2006), Chun
et al. (2009), Aniket and Arunachalam (2005) have used path delay fault model.
Combined transition and path delay fault model is used by Lee and Tehranipoor
(2008).
Crosstalk fault models were first developed by Gao et al. (1990) for lossy trans-
mission line system. In this model, the coupled transmission lines were first decou-
pled into a set of independent transmission line equations by linear transformations.
Then, the solutions of this decoupled equation were represented by a set of time-
varying equivalent circuits. This circuit model was implemented in a spice simulator.
Although these models were quite effective for the specific cases of high-speed Gal-
lium Arsenide integrated circuits, they are not applicable to VLSI circuits because of
the complexity of the circuit model and high computation time. Further, they provide
little insights into the coupling mechanism.
A simplified lumped RC model (Rubio et al. 1994) is assumed for crosstalk pulse
fault between a pair of coupled lines. Assuming a small wire resistance, the dis-
1.6 Crosstalk Fault Models 11

Fig. 1.4 Circuit showing

Ai A Aout
source of crosstalk due to
capacitive coupling

Cc

Vout
Vi V

tributed capacitance was modeled by a coupling capacitance between the aggressor

line denoted as A-line and victim line denoted as V-line. A layout tool is used to find
the coupling capacitance and aggressor line-to-ground capacitance. From this value,
the strength of aggressor lines which affect the victim lines was found to derive a
list of target crosstalk faults. However, crosstalk delay faults where both lines have
transitions had not been considered which is necessary for high-performance system.
To overcome this limitation, a model is developed by Chen et al. (1999) to evaluate
the effect of parasitic coupling crosstalk where inputs to one or both coupled lines
have transitions with arbitrary transition times and directions. All CMOS logic gates
were modeled as equivalent inverters, and then, the output response of crosstalk noise
was calculated through this gate using the transfer function of the equivalent inverter.
Figure 1.4 shows the source of crosstalk due to capacitive coupling. CC denotes the
coupling capacitance between the A-line and V-line.
The lumped model of coupling capacitance is shown in Fig. 1.5. The resistances
Ra1 and Ra2 are the line resistance and on-channel resistance associated with the line
driver, respectively. C 1 and C 2 denote line capacitance and gate capacitance of the
load driven by the line, respectively. The coupling network consists of C C , C 1 , and
C 2 . Figure 1.5 consists of three stages: input stage, a driver stage made of pulling
resistances, and the coupling network. Laplace transform is used for all three stages,
and an expression is obtained in the frequency domain, which can be transformed to
time domain. From these equations, the crosstalk effects that should be considered
for validation and test generation are identified. This model had been used for both
crosstalk pulse and delay analysis (Chen et al. 1997). However, this model is very
computationally intensive and takes a long time to simulate a small circuit.
Maximum aggressor (MA) fault model is suggested by Rubio et al. (1994) for
crosstalk which takes only the coupling capacitances into account. All aggressors
are assumed to make simultaneous transitions in the same direction while the victim
makes an opposite transition.
A constrained path delay fault (CPDF) model is used in Krstic et al. (2001). In
this model, the fault is defined as the critical path and a set of interconnects coupled
to it. Critical paths are paths whose delay is longer than a specified percentage of
the longest propagation delay in the circuit. A statistical timing analysis framework
was used for target fault selection phase. In statistical timing analysis, the delays of
cells/interconnects are modeled as correlated random variables with known proba-
12 1 Introduction

Fig. 1.5 Capacitive Ra1

coupling model A
Ai
C1
Ra2 Cc
Vi
C2
V

bility density functions. Using the cell delays, the cell-level net list and the clock
period, statistical timing analysis can derive the probability density functions of the
signal arrival times, required times, and slacks at internal signals and primary out-
puts. Using this information, the noise sources resulting in sensitivity higher than a
certain threshold are found. By intersecting the obtained noise sources and the set
of critical paths chosen without taking into account noise effects, set of crosstalk
faults is obtained. Each crosstalk fault consists of a path and a set of noise sources
interacting with the path. Exact delay information was not available in the CPDF
model. Hence, the time of transitions and the sub-paths from which the aggressor
transitions can be activated are unknown.
A coupled transition fault model (CTF) is used by Takahashi et al. (2005). A single
victim/aggressor crosstalk fault is considered. Four possible crosstalk delay faults
are considered. They are simultaneous rising or falling which are crosstalk-induced
speedup faults, one rising and another falling, and vice versa, which is crosstalk-
induced slowdown faults. This model uses a slow-fast-slow clock method to test
crosstalk delay faults in sequential circuits. The sequential circuit is expressed as an
iterative array model. In this model, crosstalk fault was induced in the victim line
when necessary conditions to excite the fault occur on the aggressor line. To calculate
the number of target faults, the static timing analysis algorithm uses structural and
timing information. False crosstalk faults that need not be tested were identified.
A single precise crosstalk-induced path delay fault model (S-PCPDF) is developed
by Li et al. (2006). In this path delay fault model, only robust paths are considered.
Crosstalk delay faults associated with robust path are taken as target faults. A crosstalk
fault is a path delay fault that is caused by a coupling effect between A-line and a
V-line on path denoted as p, such that there exists a sub-path denoted as sp-A starting
from the primary input and ending at line A-line and a sub-path denoted as sp-V
ending at V-line, satisfying the following conditions:
1. The difference in delay of the sp-V and sp-A should be within a specified interval.
2. The parity of the number of inverter gates on sp-A is different from the parity of
the number of inverter gates on sp-V.
1.6 Crosstalk Fault Models 13

An S-PCPDF can be represented using a 4-tuple (p, sp-A, V-line, A-line), while
p is usually a critical path, A-line is the aggressor line, V-line is the victim line,
and sp-A is the sub-path that propagates the aggressor transition to A-line. A single
precise crosstalk-induced path delay fault model (S-PCPDF) was developed by Li
et al. (2005) for non-robust paths.

1.7 Conclusion

The current scenario in VLSI testing and the test challenges in deep submicron
technologies is discussed in this chapter. The phenomena of unwanted crosstalk
pulses, crosstalk models at circuit level and gate level, and the various crosstalk
delay faults have also been presented.

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14 1 Introduction

H.S. Gao, A.T. Yang, S.M. Kang, Modeling and simulation of interconnection delays and crosstalk
in high-speed integrated circuits, in IEEE Transaction on Circuits and Systems, vol. 37 (January
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Trans. Comput. Aided Des. Integr. Circ. Syst. 27(6), 1150–1154 (2008)
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J. Lee, M. Tehranipoor, A novel pattern generation framework for inducing maximum crosstalk
effects on delay-sensitive paths, in International Test Conference (IEEE, 2008)
H. Li, Y. Zhang, X. Li, Delay test pattern generation considering crosstalk-induced effects, in
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H. Li, P. Shen, X. Li, Non-robust test generation for precise crosstalk induced path delay faults, in
Proceedings of Asian Test Symposium, pp. 120–125 (2005)
H. Li, P. Shen, X. Li, Robust test generation for precise crosstalk induced path delay faults, in
Proceedings of VLSI Test Symposium, pp. 300–305 (2006)
F. Moll, A. Rubio, Spurious signals in digital CMOS VLSI circuits: a propagation analysis. IEEE
Trans. Circ. Syst. II Analog Digital Signal Process. 39(10), 749–752 (1992)
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between on-chip coupled interconnects, in Proceedings of 11th Electronics Packaging Technology
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faults in digital VLSI circuits, in IEEE Transactions on Computer Aided Design of Integrated
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delay faults, in Proceedings of the 12th Asian Test Symposium (2003)
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Chapter 2
Delay Fault Testing of VLSI Circuits

2.1 Introduction

The advances in VLSI technology have resulted in devices with millions of transistors
thus creating new test challenges. Moore’s law states that the scale of ICs has doubled
every 18 months. Reduction in feature size increases the speed of integrated circuits,
thus increasing the probability that a manufacturing defect in the IC will result in a
faulty chip.
Some manufacturing defects do not change the steady-state logical operation of
a system, but they may affect the timing behavior of a system and degrade overall
system timing performance and hence industry is forced to test timing anomalies in
circuits. The purpose of delay testing is to identify timing defects so that the design
adheres to the desired performance specifications. The need for delay testing is further
expected to grow with the current design trend of moving toward deep submicron
devices. Imprecise delay modeling, statistical variations of the parameters during
the manufacturing process, and physical defects in integrated circuits can sometimes
degrade circuit performance without altering its logic functionality. Delay testing
has been a topic of extensive research both in industry and in academia. Earlier delay
defects could be detected using tests for gross delay defects. Aggressive timing
requirements of high-speed designs have introduced the need to test smaller timing
defects and distributed faults caused by statistical timing variations.
The problems in delay fault testing are as follows:
• Testing of sequential circuits results in high area overhead and large execution
times.
• Requirement of high-speed testers.
• Small distributed defects require path delay model which requires testing of very
large number of paths for complex, large circuits.
• Critical path selection.

© Springer Science+Business Media Singapore 2019 15

S. Jayanthy and M. C. Bhuvaneswari, Test Generation of Crosstalk Delay
Faults in VLSI Circuits, https://doi.org/10.1007/978-981-13-2493-2_2
16 2 Delay Fault Testing of VLSI Circuits

• All paths cannot be sensitized and hence will result in a poor fault coverage.
• Design and synthesis techniques result in high area and large number of primary
inputs.
The reasons for timing failures in combinational circuits are excessive propagation
delay, correct output appears later than specified, inadequate propagation delay, cor-
rect output appears sooner than specified and static or dynamic hazards may appear
at the outputs. The basis for timing failures in sequential circuits are excessive prop-
agation delay, setup time (long path) violation, inadequate propagation delay and
hold time (short path) violation.

2.2 Delay Fault Models

Delay fault testing is back-end process which ensures that the product quality meets
established standards in terms of performance and physical defects. Defects in the
manufacturing process often result in propagation delays to fall outside the design
requirements. The effect of these performance degrading effects can be presented
using logical fault models. It is very important that these fault models clearly and
adequately understand the environment under which defects manifest.
Delay fault models can be primarily categorized into five types.

2.2.1 Transition Fault Model

This model considers a gross delay in every gate terminal in the circuit and assumes
that the additional delay is large enough to cause a logic failure (Waicukauski et al.
1987). The transition fault model is similar to the stuck-at fault model. There are two
types of transition delay faults: a slow-to-fall fault and slow-to-rise fault associated
with each gate. A slow-to-rise fault means that any transition from 0 to 1 on a node
does not produce the correct result when the device is operating at its maximum
operating frequency. Likewise, a slow-to-fall fault means that a transition from 1 to
0 does not produce the correct result at the desired frequency. In a fault-free circuit,
each gate has a nominal rise and fall delay. If there are delay faults, then the nominal
delay will increase. The size of the gate-level delay fault must be such that it exceeds
the slack of at least one path from the fault site to the primary output or scan flip-flop
such that the fault can be observed at the output.
The main advantage of the transition fault model is that the number of faults in
the circuit is small. Further, the existing test generation and fault simulation tools for
stuck-at faults can be modified for testing transition delay faults.
A test for a transition fault is a pair of input vectors which consists of one initial-
ization vector to set up the initial state of a transition and the second vector activates
2.2 Delay Fault Models 17

X,0 a
f

0,1 b

e
o
X,1 c

X,1 d
g

Fig. 2.1 Circuit with transition fault

the fault and propagates its effect to some primary output. The propagation vector is
identical to the pattern that detects the corresponding stuck-at fault.
The transition fault coverage is a measure of the efficiency of the delay test in
detecting large delay variations. Transition faults are a special case of gate delay
faults because the delay due to the defect is large enough to cause a logical failure
when propagated along any path through the site of the fault. The disadvantage is
that the assumption that one gate in the circuit is effected is not realistic. Several
delay faults together may be large enough to affect the performance of the circuit.
The transition fault model is normally used as a qualitative delay model, and circuit
delays are not considered in deriving tests.
It is known that a rising (falling) transition fault is detected if and only if: (i) The
first pattern places a 0/1 at the fault site and (ii) the second pattern detects a stuck-at-0
(stuck-at-1) fault at the transition fault site. In the circuit as shown in Fig. 2.1, to
detect a slow to rise fault in node b, vector 1: sets node b to 0, vector 2: sets the node
b to 1 (to detect s-a-0). So if there is fault in node b, the node will not change to 1.
Now, when the output e is read, the output will not change to 1. It will remain at 0.
Hence, a slow-to-rise fault manifests itself into a stuck-at-0 fault when a two vector
test is applied and if the delay fault is large enough. Further, the observation time at
the primary output should be longer than a predefined interval.

2.2.2 Gate Delay Fault Model

The gate delay fault model assumes that the delay fault is lumped at one gate in
the circuit. A localized timing failure at a gate causes the propagation delay of at
least one path in the circuit through the fault site to exceed the specified cycle time.
This model assumes that delays of logic gates are known with some precision. On
the other hand, the gate delay fault model does not assume that the increased delay
will affect the performance independent of the propagation path through the fault
18 2 Delay Fault Testing of VLSI Circuits

5
(a) (b)

S0

Fig. 2.2 a Circuit not considering timing, b circuit with timing information

0 1
A E
2 6

C 2

F
2 2
2
B
6 8 10 12
0 D 1

Fig. 2.3 Circuit with delay fault at the output

site. It assumes that only long paths through the fault model will cause performance
degradation. It is a quantitative model that takes the circuit delays into account. The
number of faults is linear to the number of gates in the circuit. Similar to a transition
fault model, the disadvantage of this model is that the test may fail to detect delay
faults that are sum of several small delay effects. Figure 2.2a shows the AND gate.
If the information about the gate delays is not available, it is assumed that a static
hazard may prevent the propagation of some fault. If the information of the delays are
available and if the arrival time of the signals at the input are as shown in Fig. 2.2b,
the output will have a stable 0 which may propagate some fault to the primary output
(Krstic and Cheng 1998).
Figure 2.3 shows the problem with gate delay modeling. The delays of the gate
are as shown in the figure. At C, there is a slow-to-rise fault. As the value of C rises to
1, the output becomes high through shortest path with a delay of 6 time units. After
a delay of 2 time units, through the lower NOR gate the output goes back to logic 0
because output of NOR gate is logic 0. Again output goes to logic 1 taking the critical
path through the circuit at 10 time units as output of upper OR gate becomes logic 1.
Hence, a delay as large as time of observation of 12 units at output F is detectable. A
dynamic hazard is observed at the output due to different delays of the gates. Here,
only longest path through the circuit is considered. But a small gate delay fault is
difficult to detect because of hazards.
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Title: Nameless River

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 NAMELESS RIVER
BY
VINGIE E. ROE
Author of “Tharon of Lost Valley,” “Val of Paradise,” etc.

NEW YORK
DUFFIELD AND COMPANY
1923
 Copyright, 1923, by
THE McCALL COMPANY
Copyright, 1923, by
DUFFIELD & COMPANY
Printed in U. S. A.
 CONTENTS
I. “Fight for a Woman? Hell! If ’twas th’ Horse, Now—”
II. The Homestead on Nameless
III. The Iron Hand of Sky Line
IV. The Mystery of Blue Stone Cañon
V. What Nance Found
VI. Shadows in the Sheriff’s Glass
VII. The Shadows Thicken
VIII. Brand Fair
IX. Golden Magic
X. The Seventh Sense
XI. The Ashes of Hope
XII. “Get-out-of-that-Door!”
XIII. “We’re Our Pappy’s Own—and we Belong on Nameless.”
XIV. Light on the Sheriff’s Shadows
XV. The Flange in Rainbow Cliff
XVI. The Ancient Miracle
XVII. The Face in the Package
XVIII. The Fighting Line at Last
XIX. Riders of Portent
XX. Conclusion
NAMELESS RIVER
 CHAPTER I
“FIGHT FOR A WOMAN? HELL! IF ’TWAS TH’ HORSE NOW—”

It was Springtime in the Deep Heart country. On the broad slopes,

the towering slants of the hills themselves, the conifers sang their
everlasting monotone, tuned by the little winds from the south.
On the flaring fringes of their sweeping skirts where the streams
ran, maples trembled in the airy sun and cottonwoods shook their
thousand palms of silver.
Great cañons cut the ridges, dark and mysterious, murmuring
with snow water, painted fantastically in the reds and browns and
yellows of their weathered stone. Pine trees grew here, and piñons,
hemlock and spruce, all the dark and sombre people of the forest,
majestic and aloof.
But in the sweet valleys that ran like playful fingers all ways
among the hills, where lay tender grass of a laughing brightness,
flowers nodded thick in the drowsy meadows. It was a lonesome
land, set far from civilization, but beautiful withal, serene, silent, wild
with crag and peak and precipice. Deer browsed in its sheltered
places, a few timber wolves preyed on them, while here and there a
panther screamed to the stars at night.
For many years a pair of golden eagles had reared their young on
the beetling escarpment that crowned Mystery Ridge.
It was a rich land, too, for many cattle ran on its timbered slants
and grew sleek and fat for fall along the reaches of the river.
On a day when all the world seemed basking in the tempered sun,
a horse and rider came down along the slopes heading toward the
west. On the broad background of this primeval setting they made a
striking picture, one to arrest the eye, for both were remarkable. Of
the two, perhaps the horse would first have caught the attention of
an observer, owing to its great stature and its shining mouse-blue
coat.
Far off, also, the prideful grace of its carriage, the lightness, the
arrogance of its step, would have been noticeable. But as they drew
near, one looked instinctively to see what manner of rider bestrode
so splendid a fellow, and was not disappointed—for the rider was a
woman.
She was a gallant woman, if one could so describe her, not large
but built with such nicety of line, of proportion, as best to show off
the spirit in her—and that was a thing which might not be described.
Under her sombrero, worn low on her brow and level, one got the
seeming of darkness shot with fire—the black eyes and bit of dusky
hair above cheeks brightly flushed. She rode at ease, her gauntleted
hands clasped on her pommel, her reins swinging. A blue flannel
shirt, gay with pearl buttons, lay open at the throat and bloused a
trifle above a broad leather belt, well worn and studded with nickel
spots. A divided skirt of dark leather, precisely fitted and deeply
fringed at the bottom, concealed the tops of high laced boots. All her
clothing betokened especial make, and very thorough wear.
As the blue horse sidled expertly down the slope a loose stone
turned under his shod hoof, causing him to stumble ever so slightly,
though he caught himself instantly.
As instantly the woman’s spurred heel struck his flank, her swift
tightening of the rein anticipated his resultant start.
“Pick up your feet, you!” she said sharply, frowning.
The stallion did pick up his feet, for he was intelligent, but he
shook his proud head, laid his ears back on his neck, and the sweat
started on his sensitive skin at the needless rake of the spur. The
great dark eyes in his grey-blue face shone for a time like fox-fire in
the dark, twin sparks beneath the light of his tossing silver forelock.
He choose his footing more carefully, though he was an artist in
hill climbing at all times, for the woman on his back was a hard task-
master. Caught as a colt in the high meadows of the Upper Country
beyond the Deep Heart hills, the horse had served her faithfully for
four of his seven years of life, and hated her sullenly. There was
mixed blood in his veins—wild, from the slim white mother who had
never felt a rope, patrician, gentle, tractable, from the thoroughbred
black father lost from a horse-trader’s string eleven years back and
sought for many bootless moons because of his great value.
Swayed by the instincts of these two strains the superb animal
obeyed this woman who was unquestionably his master, though
rebellion surged in him at every chastisement.
The sun was at the zenith, marking the time of short shadows,
and its light fell in pale golden washes over the tapestried green
slopes. Tall flowers nodded on slim stalks in nook and crevasse—frail
columbine and flaming bleeding hearts—and mosses crept in the
damp places.
For an hour the two came down along the breast of a ridge,
dropping slowly in a long diagonal, and presently came out on a bold
shoulder that jutted from the parent spine. Here, with the thinning
trees falling abruptly away, a magnificent view spread out below. For
a long time there had been in the rider’s ears a low and heavy
murmur, a ceaseless sound of power. Now its source was visible—the
river that wound between wide meadows spread like flaring flounces
on either side—broad, level, green stretches that looked rich as a
king’s lands, and were.
The woman reined up her horse and sitting sidewise looked down
with moody eyes. A frown drew close the dark brows under the hat
brim, the full sensuous lips hardened into a tight line.
Hatred flamed in her passionate face, for the smiling valley was
tenanted. At the far edge of the green floor across the river there
nestled against the hills that rose abruptly the small log buildings of
a homestead. There was a cabin, squarely built and neat, a stable, a
shed or two, and stout corrals, built after the fashion of a stockade,
their close-set upright saplings gleaming faintly in the light.
And on the green carpet a long brown line lay stretched from end
to end, straight as a plumb-line, attesting to the accuracy of the eye
that drew it. A team of big bay horses even now plodded along that
line, leaving behind them a tiny addition in the form of a flange of
new turned earth, the resistless effect of the conquering plow.
 The plow, hated of all those who follow the fringe of the
wilderness, savage, trapper, and cattleman.
In the furrow behind walked the owner of the accurate eyes—
deep, wide, blue eyes they were, set beautifully apart under calm
brows of a golden bronze which matched exactly the thick lashes
and the heavy rope of hair braided and pinned around the head
hidden in an old-fashioned sunbonnet—for this only other figure in
the primeval picture was a woman also. She was young by the grace
of the upright carriage, strong by the way she handled her plow,
confident in every movement, every action. She stood almost as tall
as the average man, and she walked with the free swing of one.
For a long time the rider on the high shoulder of the ridge sat
regarding these tiny plodders in the valley.
Then she deliberately took from its straps the rifle that hung on
her saddle, lifted it to her shoulder, took slow aim and fired. It was a
high-power gun, capable of carrying much farther than this point of
aim, and its bullet spat whiningly into the earth so near the moving
team that one of the horses jumped and squatted.
The woman lowered the gun and watched.
But the upright figure plodding in its furrow never so much as
turned its head. It merely pulled the lines buckled about its waist,
thereby steadying the frightened horse back to its business, and
crept ahead at its plowing.
“Damn!” said the woman.
She laid the rifle across her pommel, reined the blue stallion
sharply away and went on her interrupted journey.

Two hours later she rode into the shady, crooked lane that passed
for a street in Cordova. Composed of a general store, a blacksmith-
shop, a few ancient cabins, the isolated trading point called itself a
town. McKane of the store did four-ply business and fancied himself
exceedingly.
As the woman came cantering down the street between the
cabins he ceased whittling on the splinter in his hands and watched
her. She was well worth watching, too, for she was straight as an
Indian and she rode like one. Of the half-dozen men lounging on the
store porch in the drowsy afternoon, not one but gazed at her with
covetous eyes.
A light grew up in McKane’s keen face, a satisfaction, an
appreciation, a recognition of excellence.
“By George!” he said softly. “Boys, I don’t know which is the most
worth while—the half-breed Bluefire or Kate Cathrew on his back!”
“I’ll take the woman,” said a lean youth in worn leather, his
starved young face attesting to the womanless wilderness of the
Upper County from whence he hailed. “Yea, Lord—I’ll take the
woman.”
“You mean you would,” said McKane, smiling, “if you could. Many
a man has tried it, but Kate rides alone. Yes, and rules her kingdom
with an iron hand—that’s wrong—it’s steel, and Toledo steel at that,
tempered fine. And merciless.”
“You seem to know th’ lady pretty well.”
“All Nameless River knows her,” said the trader, lowering his voice
as she drew near, “and the Deep Hearts, too, as far as cattle run.”
“Take an’ keep yer woman—if ye can—” put in a bearded man of
fifty who sat against a post, this booted feet stretched along the
floor, “but give me th’ horse. I’ve loved him ever sence I first laid
eyes on him two years back.
“He’s more than a horse—he’s got brains behind them speakin’
eyes, soft an’ black when he’s peaceful, but burnin’ like coals when
he’s mad. I’ve seen him mad, an’ itched to own him then. Kate’s a
brute to him—don’t understand him, an’ don’t want to.”
McKane dropped his chair forward and rose quickly to his feet as
the woman cantered up.
“Hello, Kate,” he said, as she sat a moment regarding the group,
“how’s the world at Sky Line Ranch?”
“All there,” she said shortly, “or was when I left.”
She swung out of her saddle and flung her reins to the ground.
She pulled off her gloves and pushed the hat back from her
forehead, which showed sweated white above the tan of her face.
She passed into the store with McKane, the spurs rattling on her
booted heels.
Left alone the big, blue stallion turned his alert head and looked
at the men on the porch, drawing a deep breath and rolling the
wheel in his half-breed bit.
It was as the bearded man had said—intelligence in a marked
degree looked out of the starry eyes in the blue face. That individual
reached out a covetous hand, but the horse did not move. He knew
his business too well as Kate Cathrew’s servant.
Inside the store the woman took two letters which McKane gave
her from the dingy pigeonholes that did duty as post office, read
them, frowned and put them in the pocket of her leather riding skirt.
Then she selected a few things from the shelves which she stowed
in a flour-sack and was ready to go. McKane followed her close, his
eyes searching her face with ill-concealed desire. She did not notice
the men on the porch, who regarded her frankly, but passed out
among them as though they were not there. It was this cool
insolence which cleared the path before her wherever she appeared,
as if all observers, feeling the inferiority her disdain implied,
acknowledged it.
But as she descended the five or six steps that led down from the
porch, she came face to face with a newcomer, one who neither
gaped nor shifted back, but looked her square in the face.
This was a man of some thirty-four or five, big, brawny, lean and
fit, of a rather homely countenance lighted by grey eyes that read
his kind like print.
He looked like a cattleman save for one thing—the silver star
pinned to the left breast of his flannel shirt, for this was Sheriff Price
Selwood.
“Good day, Kate,” he said.
A red flush rose in the woman’s face, but it was not set there by
any liking for the speaker who accosted her, that was plain.
“It’s never a good day when I meet you,” she said evenly, “it’s a
bad one.”
The Sheriff smiled.
 “That’s good,” he answered, “but some day I’ll make it better.”
McKane, his own face flushed with sudden anger, stepped close.
“Price,” he said thinly, “you and I’ve been pretty fair friends, but
when you talk to Miss Cathrew like that, you’ve got me to settle
with. That sounded like a threat.”
“Did it?” said Selwood. “It was.”
The trader was as good as his word.
With the last syllable his fist shot out and took the speaker in the
jaw, a clean stroke, timed a half-second sooner than the other had
expected, though he had expected it. It snapped his head back on
his shoulders, but did not make him stagger, and the next moment
he had met McKane half-way with all the force of his two hundred
pounds of bone and muscle.
In the midst of the whirlwind fight that followed, Kate Cathrew,
having pulled on her gloves and coolly tied her sack in place on her
saddle, mounted Bluefire and rode away without a backward look.

Twenty minutes later the Sheriff picked up the trader and rolled
him up on the porch. He stood panting himself, one hand on the
worn planking, the other wiping the blood and dirt from his face.
“Get some water, boys,” he said quietly, “and when he comes
around tell him I’ll be back tomorrow for my coffee and tobacco—
five pounds of each—and anything more he wants to give me.”
He picked up his wide hat, brushed it with his torn sleeve, set it
back on his head precisely, walked to his own horse, which was tied
some distance away, mounted and rode south toward the more open
country where his own ranch lay.
“I’m damned!” said the bearded man softly, “it didn’t take her
long to stir up somethin’ on a peaceful day! If it’d been over Bluefire,
now—there’s somethin’ to fight for—but a woman; Hell!”
“But—Glory—Glory!” whispered the lean boy who had watched
Kate hungrily, “ain’t she worth it! Oh, just ain’t she! Wisht I was
McKane this minute!”
“Druther be th’ Sheriff,” said the other enigmatically.
 CHAPTER II
THE HOMESTEAD ON NAMELESS

When the sun dropped over the western ridge, the girl in the
deep sunbonnet unhitched her horses from the plow. She looped her
lines on the hames, rubbed each sweated bay head a moment,
carefully cleaned her share with a small wooden paddle which she
took from a pocket in her calico skirt, and tipped the implement over,
share-face down.
Then she untied the slatted bonnet and took it off, carrying it in
her hand as she swung away with her team at her heels, and the
change was marvelous. Where had been a somewhat masculine
figure, plodding at man’s work a few moments before, was now a
young goddess striding the virgin earth.
The rose glow of coming twilight in the mountains bathed the
stern slants with magic, fell on her bronze head like ethereal dust of
gems. All in a moment she had become beautiful. The golden shade
of her smooth skin was put a tint above that of her hair and brows
and lashes, a blend to delight an artist, so rare was it—though her
mother said they were “all off the same piece.” There was red in her
makeup, too, faint, thinned, beneath the light tan of her cheeks,
flaming forth brightly in the even line of her full lips.
Out of this flare of noon-day color her blue eyes shone like calm
waters under summer skies. Some of the men of the country had
seen John Allison’s daughter, but not one of them would have told
you she was handsome—for not one of them had seen her without
the disfiguring shelter of the bonnet. She went with the weary
horses to the edge of the river, flat here in the broad meadows, and
stood between them as they drank.
She raised her head and looked across the swift water-stream to
the high shoulder of the distant ridge, but there was no fear in the
calm depths of her eyes. She stood so, quiet, tired, at ease, until the
horses had drunk their fill and with windy breaths of satisfaction
were ready to go on across the flat to the stable and corral.
Here she left them in the hands of a boy of seventeen, very much
after her own type, but who walked with a hopeless halt, and went
on to the cabin.
“Hello, Mammy,” she said, smiling—and if she had been beautiful
before she was exquisite when she smiled, for the red lips curled up
at the corners and the blue eyes narrowed to drowsy slits of
sweetness.
But there was no answering smile on the gaunt face of the big
woman who met her at the door with work-hardened hands laid
anxiously on her young shoulders.
“Nance, girl,” she said straightly, “I heard a shot this afternoon—I
reckon it whistled some out there in th’ field?”
“It did,” said Nance honestly, “so close it made Dan squat.”
In spite of her courage the woman paled a bit.
“My Lord A’mighty!” she said distressedly, “I do wish your Pappy
had stayed in Missouri! I make no doubt he’d been livin’ today—and
I’d not be eating my heart out with longin’ for him, sorrow over Bud,
an’ fear for you every time you’re out of my sight. And th’ land ain’t
worth it.”
But Nance Allison laid her hand over her mother’s and turned in
the doorway to look once again at the red and purple veils of dusk-
haze falling down the mountain’s face, to listen to the song of
Nameless River, hurrying down from the mysterious cañons of the
Deep Heart hills, and a sort of adoring awe irradiated her features.
“Worth it?” she repeated slowly. “No—not Papp’s death—not Bud’s
lameness—but worth every lick of work I ever can do, worth every
glorious hour I spend on it, worth every bluff I call, every sneak-thief
enemy I defy—and some day it will be worth a mint of gold when
the cattle grow to herds. And in the meantime it’s—why, Mammy, it’s
the anteroom of Heaven, the fringes of paradise, right here in
Nameless Valley.”
The mother sighed.
 “You love it a lot, don’t you?” she asked plaintively.
“I think it’s more than love,” said the big girl slowly as she rolled
her faded sleeves higher along her golden arms preparatory to
washing at the well in the yard, “I think it’s principle—a proving of
myself—I think it’s a front line in the battle of life—and I believe I’m
a mighty fighter.”
“I know you are,” said the woman with conviction, faintly tinged
with pride, “but—there’ll be few cattle left for herds if things go on
the way they have gone. Perhaps there’ll be neither herds nor
herders——”
But her daughter interrupted.
“There’ll be a fight, at any rate,” she said as she plunged her face,
man fashion, into the basin filled with water from the bucket which
she had lifted, hand over hand—“there’ll be a fight to the finish
when I start—and some day I’m afraid I’ll start.”
She looked at her mother with a shade of trouble on her frank
face.
“For two years,” she added, “I’ve been turning the other cheek to
my enemies. I haven’t passed that stage, yet. I’m still patient—but I
feel stirrings.”
“God forbid!” said the older woman solemnly, “it sounds like feud!”
“Will be,” returned the girl shortly, “though I pray against it night
and day.”
The boy Bud came up from the stable along the path, and Nance
stood watching him. There was but one thing in Nameless Valley
that could harden her sweet mouth, could break up the habitual
calm of her eyes. This was her brother, Bud.
When she regarded him, as she did now, there was always a flash
of flame in her face, a wimple of anguish passing on her features, an
explosion, as it were, of some deep and surging passion, covered in;
hidden, like molten lava in some half-dead crater, its dull surface
cracking here and there with seams of awful light which drew
together swiftly. Now for the moment the little play went on in her
face.
Then she smiled, for he was near.
 “Hello, Kid,” she said, “how’s all?”
The boy smiled back and he was like her as two peas are like
each other—the same golden skin, the same mouth, the same blue
eyes crinkling at the corners.
But there the likeness ended, for where Nance was a delight to
the eye in her physical perfection, the boy hung lopsided, his left
shoulder drooping, his left leg grotesquely bandied.
But the joy of life was in him as it was in Nance, despite his
misfortune.
“Whew!” he said, “it’s gettin’ warm a-ready. Pretty near melted
working in th’ garden today. Got three beds ready. Earth works up
fine as sand.”
“So it does in the field,” said Nance as she followed the mother
into the cabin, “it’s like mould and ashes and all the good things of
the land worked in together. It smells as fresh as they say the sea
winds smell. Each time I work it, it seems wilder and sweeter—old
lady earth sending out her alluring promise.”
“Land sakes, girl,” said Mrs. Allison, “where do you get such
fancies!”
“Where do you suppose?” said Nance, “out of the earth herself.
She tells me a-many things here on Nameless—such as the value of
patience, an’ how to be strong in adversity. I’ve never had the
schools, not since those long-back days in Missouri, but I’ve got my
Bible and I’ve got the land. And I’ve got the sky and the hills and the
river, too. If a body can’t learn from them he’s poor stuff inside.
Mighty poor.”
She tidied her hair before the tiny mirror that hung on the kitchen
wall, a small matter of passing her hands over the shining mass, for
the braids were smooth, almost as they had been when she pinned
them there before sun-up, and rolling down her sleeves, sat down to
the table where a simple meal was steaming. She bowed her head
and Mrs. Allison, her lean face gaunt with shadows of fear and
apprehension, folded her hard hands and asked the customary
blessing of that humble house.
 Humble it was in every particular—of its scant furnishings, of its
bare cleanliness which was its only adornment, of the plain food on
the scoured, clothless table.
These folk who lived in it were humble, too, if one judged only by
their toil-scarred hands, their weary faces.
But under the plain exterior there was something which set them
apart, which defied the stamp of commonplace, which bid for the
extraordinary.
This was the dominant presence of purpose in the two younger
faces, the spirit of patient courage which shone naked from the two
pairs of blue eyes.
The mother had less of it.
She was like a war-mother of old—waiting always with a set
mouth and eyes scanning the distances for tragedy.
That living spirit of stubborn courage had come out of the heart
and soul of John Allison, latter day pioneer, who for two years had
slept in a low, neat bed at the mountain’s foot beyond the cabin, his
end one of the mysteries of the wild land he had loved. His wife had
never ceased to fret for its unravelling, to know the how and
wherefore of his fall down Rainbow Cliff—he, the mountaineer, the
sure, the unchancing. His daughter and son had accepted it, laid it
aside for the future to deal with, and taken up the work which he
had dropped—the plow, the rope and the cattle brand.
It was heavy work for young hands, young brains.
The great meadow on the other side of Nameless was rich in wild
grass, a priceless possession. For five years it had produced
abundant stacks to feed the cattle over, and the cutting and stacking
was work that taxed the two to the very limit of endurance. And the
corn-land at the west—that, too, took labor fit for man’s muscles.
But there were the hogs that ran wild and made such quick fattening
on the golden grain in the early fall. It was the hogs that paid most
of the year’s debt at the trading store, providing the bare necessities
of life, and Nance could not give up that revenue, work or no work.
Heaven knew, she needed them this year more than ever—since the
fire which had flared in a night the previous harvest and taken all
three of the stacks in the big meadow. That had been disaster,
indeed, for it had forced her to sell every head of her stock that she
could, at lowest prices, leaving barely enough to get another start.
McKane had bought, but he had driven a hard bargain.
This was another spring and hope stirred in her, as it is ever prone
to do in the heart of youth.
Tired as she was, the girl brought forth from the ancient bureau in
her own room beyond, a worn old Bible, and placing it beneath the
lamp, sat herself down beside the table to the study of that Great
Book which was her classic and her school. Mrs. Allison had retired
into the depths of the cabin, from the small room adjoining, Nance
could hear the regular breathing of Bud, weary from his labors. For a
long time she sat still, her hands lying cupped around the Book, her
face pensive with weariness, her eyes fixed unwinking on the yellow
flame. Then she turned the thin pages with a reverent hand and at
the honeysweet rhythms of the Psalms, stopped and began to read.
With David she wandered afar into fields of divine asphodel, was
soon lost in a sea of spiritual praise and song.
Her young head, haloed with a golden spray in the light of the
lamp, was bent above the Bible, her lashes lay like golden circles,
sparkling on her cheeks, her lips were sweetly moulded to the words
she unconsciously formed as she read.
For a long time she pored over the ancient treasure of the
Scriptures, and in all truth she was innocent enough, lovely enough
to have stirred a heart of stone. It was warm with the breath of
spring outside. Window and door stood open and no breeze stirred
the cheap white curtain at the sill.
Peace was there in the lone homestead by the river, the security
that comes with knowledge that all is looked to faithfully. Nance
knew that the two huge padlocks on the stout log barn that housed
the horses and the two milk cows, were duly fastened, for their keys
hung on the wall beside the towel-roller. She knew that the well-
board was down, that the box was filled with wood for the early
breakfast fire.
 “‘In Thee, Oh, Lord, do I put my trust,’” she read in silence. “‘Let
me never be ashamed, deliver me in Thy righteousness——’”
She laid her temples in her palms, her elbows on the table, and
her blue eyes followed the printed lines with a rapt delight.
Suddenly she sat upright, alert, her face lifted like that of a
startled creature of the wild. She had heard no sound. There had
been no tremor of the earth to betray a step outside, and yet she
felt a presence.
She did not look toward the openings, but stared at the wall
before her with its rows of shelves behind their screened doors
where her mother kept her scoured pans.
And then, suddenly, there came a thin, keen whine, a little clear
whistle, and a knife stood quivering between her dropped hands, its
point imbedded deep in the leaves of the old Bible.
For a moment she sat so, while a flush of anger poured up along
her throat to flare to the roots of her banded hair.
With no uncertain hand she jerked the blade from the profound
pages, leapt to her feet, snatched a stub of pencil from a broken
mug on a shelf, tore a fly-leaf from the precious Book, and, bending
in the light, wrote something on it. She folded the bit of paper,
thrust the knife point through it and, turning swiftly, flung them
viciously through the window where the thin curtain had been
parted.
She stood so, facing the window defiantly, scorning to blow out
the light.
Then she dropped her eyes to the desecrated Word and they were
flaming—and this is what she had written on the fly-leaf:
“The Lord is the strength of my life—of whom shall I be afraid?
Though a host shall encamp against me, my heart shall not fear.”
Very deliberately she closed the door and window, turned locks on
both, picked up her lamp and Bible and went into her own room
beyond. Serene in the abiding faith of those divine words she soon
forgot the world and all it held of work and care, of veiled threat and
menace.
 At daybreak she opened the window and scanned the ground
outside. There was no thin-bladed knife in sight, no folded bit of
paper with its holy defiance. The whole thing might have been a
dream.
 CHAPTER III
THE IRON HAND OF SKY LINE

Kate Cathrew—Cattle Kate Cathrew—lived like an eagle, on the

crest of the world looking down. She looked down along the steep
slopes of Mystery Ridge, dark with the everlasting green of conifers,
speckled with the lighter green of glade and brush patch, the
weathered red of outcropping stone—far down to the silver thread of
Nameless River flowing between its grass-clad banks, the fair spread
of the valley with its priceless feeding land.
The buildings of Sky Line Ranch lay nestled at the foot of Rainbow
Cliff, compact, solid, like a fortress, reached only by cattle trails, for
there was no wagon road. There could have been none on these
forbidding steeps. The buildings themselves were built of logs, but
all that was within them had come into the lonesome country on
pack-mules, even to the big steel range in the kitchen. The house
itself was an amazing place, packed with all necessities, beautiful
with luxuries, its contents worth a fortune. It had many rooms and a
broad veranda circled it. Pine trees stood in ranks about it, and out
of the sheer face of Rainbow Cliff at the back a six-inch stream of
crystal water shot forth in a graceful arc from the height of a man’s
shoulder, to fall into a natural basin in the solid rock by its own
ceaseless action.
And stretching out like widespread wings on either side this
majestic cliff ran crowning the ridge for seven miles, a splendid
escarpment, straight up-and-down, averaging two hundred feet from
its base in the slanting earth to the sharp line of its rimrock.
Rainbow Cliff, grim guardian of the Upper Country and the Deep
Heart hills themselves, supposed to be impassable in all its length,
dark in the early day but gleaming afar with all the colors of the
spectrum when the sun dropped over toward the west at noon. It
was this gorgeous radiance, caused by the many shades of the
weathered stone, which had given the battlement its name. No man
was ever known to have scaled the cliff—save and except John
Allison, found dead at its foot two years back—for the giant spine
was alike on both sides. Men from the Upper Country had
penetrated the Deep Hearts to its northern base, but there they had
stopped, to circle its distant ends, void of the secrets they had
hoped to wrest from it.
And Kate Cathrew lived under it, a strange, half-sybaritic woman,
running her cattle on the slopes of Mystery, riding after them like
any man, standing in at round-up, branding, beef-gathering, her
keen eyes missing nothing, her methods high-handed. Her riders
obeyed her lightest word, though they were mostly of a type that
few men would care to handle, hard-featured, close-lipped, sharp-
eyed, hard riders and hard drinkers, as all the world of the Deep
Hearts knew.
Once in a blue moon they went to Bement, the town that lay
three days’ ride to the north beyond the hills, and what they did
there was merely hinted at. They drank and played and took
possession of its four saloons, and when they finally reared out of it
to go back to their loneliness and work, the town came out of its
temporary retirement, breathing again.
Yet Kate Cathrew handled these men and got good work out of
them, and she belonged to none of them.
Not but what there were hot hearts in the outfit and hands that
itched for her, lips that wet themselves hungrily when she passed
close in her supreme indifference.
But Rio Charley carried a bullet-scar in his right shoulder, and Big
Basford walked with a slight limp—yet they both stayed with her.
“Sort of secret-society stuff,” said Price Selwood once, “Kate is the
Grand Vizier.”
There was no other white woman at Sky Line. She would have
none. Minnie Pine, a stalwart young Pomo half-breed, and old
Josefa, brown as parchment and non-committal, carried on the
housework under her supervision, and no one else was needed.
 At noon of the day after Kate’s visit to the store at Cordova, she
sat in the big living-room at Sky Line looking over accounts. An
observer having seen her on the previous occasion, would hardly
have recognized her now. Gone were the broad hat, the pearl-
buttoned shirt, the fringed riding skirt and the boots.
The black hair was piled high on her head, its smooth backward
sweep crinkled by the tight curl that would not be brushed out.
There was fragrance about her, and the dress she wore was of dark
blue flowered silk, its clever draping setting off her form to its best
advantage, which needed no advantage. Silk stockings smoothed
themselves lovingly over her slender ankles, and soft kid slippers, all
vanity of cut and make and sparkling buckle, clothed her feet in
beauty.
She was either a fool or very brave, for she was the living spirit of
seduction.
But the sombre eyes she turned up from her work to scan the
rider who came to her, his hat in his hands, were all business,
impersonal.
“Well?” she said impatiently.
The man was young, scarce more than a boy, of a devil-may-care
type, and he looked at her fearlessly.
“Here’s something for you, Boss,” he said grinning, as he handed
her a soiled bit of paper.
It was thin, yellowed with age, and it seemed to have been
roughly handled.
The mistress of Sky Line spread it out before her on the top of the
dark wood desk.

“The Lord is the strength of my life,” she read, “of whom

shall I be afraid? Though an host shall encamp against me,
my heart shall not fear.”

It was unsigned and the characters, while hurriedly scrawled,

were made by bold strokes, as if a strong heart had, indeed, inspired
them, a strong hand penned them.
 With a full-mouthed oath Kate Cathrew crumpled the bit of paper
in her hand and flung it in the waste-basket against the wall.
“How did you get that?” she demanded.
“On the point of the knife you sent th’ girl,” he answered soberly,
“an’ right near the middle of my stomach.”
For a considerable space of time the woman sat regarding him. “I
sent you to help in the breaking of morale,” she said coldly, “not to
bring me back defiance. Next time I’ll send a more trustworthy
man.”
She nodded dismissal, and the youth went quickly, his face
burning.
At the far end of the veranda he almost ran into Big Basford,
whose huge, gorilla-like shape was made more sinister and repellant
by the perceptible limp. Basford was always somewhere near, if
possible, when men talked with Kate Cathrew.
His great strength and stature, his small eyes, black and rimmed
with red, his unkempt head and flaring black beard, everything
about him suggested a savagery and power with which few men
cared to trifle.
He scanned the boy’s flushed face with swift appraising.
“I take it,” he said grinning, “that the boss wasn’t pleased with
you?”
“Take it or leave it,” said the other with foolhardy daring, “is it any
of your business?”
With a smothered roar Big Basford leaped for him, surprisingly
nimble on his lamed foot, surprisingly light.
He caught him by the throat and bore him backward across the
veranda’s edge, so that both bodies fell heavily on the boards of the
floor.
“You’ll find what’s my business, damn you,” gritted Big Basford;
“you——!”
He got to his knees and straddling the lad’s body came down on
his throat with all his weight in his terrible grip. At the sound of the
fall Minnie Pine leaped to a window.
 “That black devil is killing the Blue Eyes,” she said in patois
Spanish to Josefa. “Give me that knife——”
But there was no need of Minnie’s interference.
Kate Cathrew had heard that heavy thunder of falling bodies on
boards and she was quicker than her half-breed, for she was up and
away from the desk before Big Basford had risen on his knees, and
as she rose her left hand swept down the wall, taking from its two
pegs the heavy quirt that always hung there.
With the first jab of the boy’s head back on the floor, she was
running down the veranda, her arm raised high. With the second she
was between Big Basford and the light like a threat of doom.
As he surged forward once more above the blackening face in his
throttling fingers, she flung her body back in a stiff arc to get more
impetus—and drove the braided lash forward and down like a fury.
It circled Big Basford’s head from the back, the bitter end
snapping across his face with indescribable force.
It curled him away from his victim, tumbling back on his heels
with his murderous hands covering his cheeks.
For a moment he hung on the veranda’s edge, balanced, then
slipped off, lurching on his lame foot. He held his hands over his face
for a tense moment. Then he looked up through his fingers, where
the blood was beginning to ooze, straight at the woman.
The red-rimmed eyes were savage with rage and hurt, but behind
both was a flaming passion which seemed to swell and burgeon with
a perverted admiration.
“I’ve told you before, Basford,” said Kate Cathrew, “that I will deal
with my men myself. I don’t need your overly zealous aid. Get out of
my sight—and stay out till you can heed what I say. Minnie, take this
fool away—pump some wind into him. Give him some whiskey.”
She touched the boy contemptuously with the toe of her buckled
slipper. He was weakly trying to get up and the Pomo girl
unceremoniously finished the effort, lifting him almost bodily in her
arms and supporting him through the door into the kitchen. The look
she turned over her shoulder at Big Basford was venomous.
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