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 Brock J. LaMeres

Introduction to Logic
Circuits & Logic Design
with Verilog

Third Edition
INTRODUCTION TO LOGIC CIRCUITS &
LOGIC DESIGN WITH VERILOG
INTRODUCTION TO LOGIC CIRCUITS &
LOGIC DESIGN WITH VERILOG
3 RD E DITION

Brock J. LaMeres
Brock J. LaMeres
Department of Electrical & Computer Engineering
Montana State University
Bozeman, MT, USA

ISBN 978-3-031-43945-2 ISBN 978-3-031-43946-9 (eBook)

https://doi.org/10.1007/978-3-031-43946-9

# The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2017,
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Preface
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom-integrated circuits, which
are cost and time prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly Field
Programmable Gate Arrays (FPGAs). This spurred an abundance of textbooks to be authored teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the “compile & synthesize” button of their design tool. This leads to graduates who can
model a breadth of different systems in an HDL but have no depth into how the system is implemented in
hardware. This becomes problematic when an issue arises in a real design and there is no foundational
knowledge for the students to fall back on in order to debug the problem.

This new book addresses the lower-level foundational void by providing a comprehensive, bottoms-
up, coverage of digital systems. The book begins with a description of lower-level hardware including
binary representations, gate-level implementation, interfacing, and simple combinational logic design.
Only after a foundation has been laid in the underlying hardware theory is the Verilog language
introduced. The Verilog introduction gives only the basic concepts of the language in order to model,
simulate, and synthesize combinational logic. This allows the students to gain familiarity with the
language and the modern design approach without getting overwhelmed by the full capability of the
language. The book then covers sequential logic and finite state machines at the structural level. Once
this secondary foundation has been laid, the remaining capabilities of Verilog are presented that allow
sophisticated, synchronous systems to be modeled. An entire chapter is then dedicated to examples of
sequential system modeling, which allows the students to learn by example. The second part of the
textbook introduces the details of programmable logic, semiconductor memory, and arithmetic circuits.
The book culminates with a discussion of computer system design, which incorporates all of the

v
vi • Preface

knowledge gained in the previous chapters. Each component of a computer system is described with an
accompanying Verilog implementation, all while continually reinforcing the underlying hardware beneath
the HDL abstraction.

Written the Way It Is Taught

The organization of this book is designed to follow the way in which the material is actually learned.
Topics are presented only once sufficient background has been provided by earlier chapters to fully
understand the material. An example of this learning-oriented organization is how the Verilog language is
broken into two chapters. Chapter 5 presents an introduction to Verilog and the basic constructs to model
combinational logic. This is an ideal location to introduce the language because the reader has just
learned about combinational logic theory in Chap. 4. This allows the student to begin gaining experience
using the Verilog simulation tools on basic combinational logic circuits. The more advanced constructs of
Verilog such as sequential modeling and test benches are presented in Chap. 8 only after a thorough
background in sequential logic is presented in Chap. 7. Another example of this learning-oriented
approach is how arithmetic circuits are not introduced until Chap. 12. While technically the arithmetic
circuits in Chap. 12 are combinational logic circuits and could be presented in Chap. 4, the student does
not have the necessary background in Chap. 4 to fully understand the operation of the arithmetic
circuitry, so its introduction is postponed.

This incremental, just-in-time presentation of material allows the book to follow the way the material
is actually taught in the classroom. This design also avoids the need for the instructor to assign sections
that move back and forth through the text. This not only reduces course design effort for the instructor but
allows the student to know where they are in the sequence of learning. At any point, the student should
know the material in prior chapters and be moving toward understanding the material in
subsequent ones.
An additional advantage of this book’s organization is that it supports giving the student hands-on
experience with digital circuitry for courses with an accompanying laboratory component. The flow is
designed to support lab exercises that begin using discrete logic gates on a breadboard and then move
into HDL-based designs implemented on off-the-shelf FPGA boards. Using this approach to a laboratory
experience gives the student experience with the basic electrical operation of digital circuits, interfacing,
and HDL-based designs.

Learning Outcomes
Each chapter begins with an explanation of its learning objective followed by a brief preview of the
chapter topics. The specific learning outcomes are then presented for the chapter in the form of concise
statements about the measurable knowledge and/or skills the student will be able to demonstrate by the
end of the chapter. Each section addresses a single, specific learning outcome. This eases the process
of assessment and gives specific details on student performance. There are over 1000 assessment tools
in the form of exercise problems and concept check questions that are tied directly to specific learning
outcomes for both formative and summative assessment.

Teaching by Example
With nearly 250 worked examples, concept checks for each section, 200+ supporting figures, and
1000+ assessment problems, students are provided with multiple ways to learn. Each topic is described
in a clear, concise written form with accompanying figures as necessary. This is then followed by
annotated worked examples that match the form of the exercise problems at the end of each chapter.
Additionally, concept check questions are placed at the end of each section in the book to measure the
 Preface • vii

student’s general understanding of the material using a concept inventory assessment style. These
features provide the student multiple ways to learn the material and build an understanding of digital
circuitry.

Course Design
The book can be used in multiple ways. The first is to use the book to cover two, semester-based
college courses in digital logic. The first course in this sequence is an introduction to logic circuits and
covers Chaps. 1, 2, 3, 4, 5, 6, and 7. This introductory course, which is found in nearly all accredited
electrical and computer engineering programs, gives students a basic foundation in digital hardware and
interfacing. Chapters 1, 2, 3, 4, 5, 6, and 7 only cover relevant topics in digital circuits to make room for a
thorough introduction to Verilog. At the end of this course, students have a solid foundation in digital
circuits and are able to design and simulate Verilog models of concurrent and hierarchical systems. The
second course in this sequence covers logic design using Chaps. 8, 9, 10, 11, 12, 13, and 14. In this
second course, students learn the advanced features of Verilog such as procedural assignments,
sequential behavioral modeling, system tasks, and test benches. This provides the basis for building
larger digital systems such as registers, finite state machines, and arithmetic circuits. Chapter 13 brings
all of the concepts together through the design of a simple 8-bit computer system that can be simulated
and implemented using many off-the-shelf FPGA boards. Chapter 14 introduces the relatively complex
topic of floating-point systems.

This book can also be used in a more accelerated digital logic course that reaches a higher level of
abstraction in a single semester. This is accomplished by skipping some chapters and moving quickly
through others. In this use model, it is likely that Chap. 2 on numbers systems and Chap. 3 on digital
circuits would be quickly referenced but not covered in detail. Chapters 4 and 7 could also be covered
quickly in order to move rapidly into Verilog modeling without spending significant time looking at the
underlying hardware implementation. This approach allows a higher level of abstraction to be taught but
provides the student with the reference material so that they can delve in the details of the hardware
implementation if interested.
All exercise and concept problems that do not involve a Verilog model are designed so that they can
be implemented as a multiple choice or numeric entry question in a standard course management
system. This allows the questions to be automatically graded. For the Verilog design questions, it is
expected that the students will upload their Verilog source files and screenshots of their simulation
waveforms to the course management system for manual grading by the instructor or teaching assistant.

Instructor Resources
Instructors adopting this book can access a growing collection of supplementary learning resources
including YouTube videos created by the author, a solutions manual, a laboratory manual, and Verilog
test benches for all problems. Additional resources are made available as demand grows. The growing
library of YouTube videos can provide supplementary learning materials for students or facilitate fully
online or flipped delivery of this material. The videos are found at https://www.youtube.com/c/
DigitalLogicProgramming_LaMeres. The solutions manual contains a graphic-rich description of select
exercise problems. A complementary lab manual has also been developed to provide additional learning
activities based on both the 74HC discrete logic family and an off-the-shelf FPGA board. This manual is
provided separately from the book in order to support the ever-changing technology options available for
laboratory exercises.
viii • Preface

What’s New in the Third Edition

The third edition adds a new chapter on floating-point numbers. By popular demand, this chapter
was added to provide a more comprehensive understanding of modern computers. The chapter provides
a low-level explanation of floating-point numbers including formation, standardization, conversions, and
arithmetic operations. It then moves into Verilog modeling of basic arithmetic operations using a manual
implementation approach. An additional 35 assessment problems and 4 concept checks are included in
Chap. 14.

Bozeman, MT, USA Brock J. LaMeres

Acknowledgments

For my mom (Kathleen). Thank you for the life you have given me. Your love and support have
always been a constant that I can count on in good times and bad. Your positivity is contagious
and touches everyone around you. You have blessed me with your patience and sense of humor,
both of which have made this life much more enjoyable. I love you.

ix
Contents
1: INTRODUCTION: ANALOG VERSUS DIGITAL ...................................................... 1
1.1 DIFFERENCES BETWEEN ANALOG AND DIGITAL SYSTEMS .................................................. 1
1.2 ADVANTAGES OF DIGITAL SYSTEMS OVER ANALOG SYSTEMS ............................................ 3
2: NUMBER SYSTEMS ................................................................................................. 7
2.1 POSITIONAL NUMBER SYSTEMS ..................................................................................... 7
2.1.1 Generic Structure ............................................................................................. 8
2.1.2 Decimal Number System (Base 10) ................................................................ 9
2.1.3 Binary Number System (Base 2) ..................................................................... 9
2.1.4 Octal Number System (Base 8) ...................................................................... 10
2.1.5 Hexadecimal Number System (Base 16) ........................................................ 10
2.2 BASE CONVERSION ..................................................................................................... 11
2.2.1 Converting to Decimal ..................................................................................... 11
2.2.2 Converting from Decimal ................................................................................. 14
2.2.3 Converting Between 2n Bases ........................................................................ 18
2.3 BINARY ARITHMETIC .................................................................................................... 22
2.3.1 Addition (Carries) ............................................................................................. 22
2.3.2 Subtraction (Borrows) ...................................................................................... 23
2.4 UNSIGNED AND SIGNED NUMBERS ................................................................................. 25
2.4.1 Unsigned Numbers .......................................................................................... 25
2.4.2 Signed Numbers .............................................................................................. 26
3: DIGITAL CIRCUITRY AND INTERFACING .............................................................. 43
3.1 BASIC GATES ............................................................................................................. 43
3.1.1 Describing the Operation of a Logic Circuit .................................................... 43
3.1.2 The Buffer ........................................................................................................ 45
3.1.3 The Inverter ...................................................................................................... 46
3.1.4 The AND Gate ................................................................................................. 46
3.1.5 The NAND Gate .............................................................................................. 47
3.1.6 The OR Gate ................................................................................................... 47
3.1.7 The NOR Gate ................................................................................................. 47
3.1.8 The XOR Gate ................................................................................................. 48
3.1.9 The XNOR Gate .............................................................................................. 49
3.2 DIGITAL CIRCUIT OPERATION ........................................................................................ 50
3.2.1 Logic Levels ..................................................................................................... 51
3.2.2 Output DC Specifications ................................................................................ 51
3.2.3 Input DC Specifications ................................................................................... 53
3.2.4 Noise Margins .................................................................................................. 53
3.2.5 Power Supplies ................................................................................................ 54
3.2.6 Switching Characteristics ................................................................................ 56
3.2.7 Data Sheets ..................................................................................................... 57

xi
xii • Contents

3.3 LOGIC FAMILIES .......................................................................................................... 62

3.3.1 Complementary Metal Oxide Semiconductors (CMOS) ................................. 62
3.3.2 Transistor-Transistor Logic (TTL) .................................................................... 71
3.3.3 The 7400 Series Logic Families ...................................................................... 73
3.4 DRIVING LOADS .......................................................................................................... 77
3.4.1 Driving Other Gates ......................................................................................... 77
3.4.2 Driving Resistive Loads ................................................................................... 79
3.4.3 Driving LEDs .................................................................................................... 81
4: COMBINATIONAL LOGIC DESIGN ......................................................................... 93
4.1 BOOLEAN ALGEBRA ..................................................................................................... 93
4.1.1 Operations ....................................................................................................... 94
4.1.2 Axioms ............................................................................................................. 94
4.1.3 Theorems ......................................................................................................... 95
4.2 COMBINATIONAL LOGIC ANALYSIS .................................................................................. 111
4.2.1 Finding the Logic Expression from a Logic Diagram ...................................... 111
4.2.2 Finding the Truth Table from a Logic Diagram ................................................ 112
4.2.3 Timing Analysis of a Combinational Logic Circuit ........................................... 113
4.3 COMBINATIONAL LOGIC SYNTHESIS ................................................................................ 115
4.3.1 Canonical Sum of Products ............................................................................. 115
4.3.2 The Minterm List (Σ) ........................................................................................ 116
4.3.3 Canonical Product of Sums (POS) .................................................................. 118
4.3.4 The Maxterm List (Π) ....................................................................................... 120
4.3.5 Minterm and Maxterm List Equivalence .......................................................... 122
4.4 LOGIC MINIMIZATION .................................................................................................... 124
4.4.1 Algebraic Minimization ..................................................................................... 124
4.4.2 Minimization Using Karnaugh Maps ................................................................ 125
4.4.3 Don’t Cares ..................................................................................................... 137
4.4.4 Using XOR Gates ............................................................................................ 138
4.5 TIMING HAZARDS AND GLITCHES ................................................................................... 141
5: VERILOG (PART 1) .................................................................................................. 153
5.1 HISTORY OF HARDWARE DESCRIPTION LANGUAGES ......................................................... 154
5.2 HDL ABSTRACTION ..................................................................................................... 157
5.3 THE MODERN DIGITAL DESIGN FLOW ............................................................................ 160
5.4 VERILOG CONSTRUCTS ................................................................................................ 163
5.4.1 Data Types ....................................................................................................... 164
5.4.2 The Module ...................................................................................................... 168
5.4.3 Verilog Operators ............................................................................................. 171
5.5 MODELING CONCURRENT FUNCTIONALITY IN VERILOG ...................................................... 176
5.5.1 Continuous Assignment .................................................................................. 176
5.5.2 Continuous Assignment with Logical Operators ............................................. 176
5.5.3 Continuous Assignment with Conditional Operators ...................................... 177
5.5.4 Continuous Assignment with Delay ................................................................. 179
 Contents • xiii

5.6 STRUCTURAL DESIGN AND HIERARCHY ........................................................................... 182

5.6.1 Lower-Level Module Instantiation .................................................................... 182
5.6.2 Gate Level Primitives ....................................................................................... 184
5.6.3 User-Defined Primitives ................................................................................... 185
5.6.4 Adding Delay to Primitives .............................................................................. 186
5.7 OVERVIEW OF SIMULATION TEST BENCHES ..................................................................... 187
6: MSI LOGIC ................................................................................................................ 193
6.1 DECODERS ................................................................................................................. 193
6.1.1 Example: One-Hot Decoder ............................................................................ 194
6.1.2 Example: 7-Segment Display Decoder ........................................................... 196
6.2 ENCODERS ................................................................................................................. 200
6.2.1 Example: One-Hot Binary Encoder ................................................................. 200
6.3 MULTIPLEXERS ............................................................................................................ 202
6.4 DEMULTIPLEXERS ........................................................................................................ 205
7: SEQUENTIAL LOGIC DESIGN ................................................................................ 211
7.1 SEQUENTIAL LOGIC STORAGE DEVICES .......................................................................... 211
7.1.1 The Cross-Coupled Inverter Pair ..................................................................... 211
7.1.2 Metastability ..................................................................................................... 212
7.1.3 The SR Latch ................................................................................................... 214
7.1.4 The S’R’ Latch ................................................................................................ 217
7.1.5 SR Latch with Enable ...................................................................................... 219
7.1.6 The D-Latch ..................................................................................................... 222
7.1.7 The D-Flip-Flop ................................................................................................ 223
7.2 SEQUENTIAL LOGIC TIMING CONSIDERATIONS .................................................................. 227
7.3 COMMON CIRCUITS BASED ON SEQUENTIAL STORAGE DEVICES ........................................ 228
7.3.1 Toggle Flop Clock Divider ................................................................................ 228
7.3.2 Ripple Counter ................................................................................................. 229
7.3.3 Switch Debouncing .......................................................................................... 230
7.3.4 Shift Registers ................................................................................................. 234
7.4 FINITE-STATE MACHINES .............................................................................................. 236
7.4.1 Describing the Functionality of an FSM .......................................................... 236
7.4.2 Logic Synthesis for an FSM ............................................................................ 238
7.4.3 FSM Design Process Overview ...................................................................... 245
7.4.4 FSM Design Examples .................................................................................... 246
7.5 COUNTERS ................................................................................................................. 254
7.5.1 2-Bit Binary Up Counter ................................................................................... 254
7.5.2 2-Bit Binary Up/Down Counter ........................................................................ 256
7.5.3 2-Bit Gray Code Up Counter ........................................................................... 258
7.5.4 2-Bit Gray Code Up/Down Counter ................................................................. 260
7.5.5 3-Bit One-Hot Up Counter ............................................................................... 262
7.5.6 3-Bit One-Hot Up/Down Counter ..................................................................... 264
7.6 FINITE-STATE MACHINE’S RESET CONDITION .................................................................. 267
xiv • Contents

7.7 SEQUENTIAL LOGIC ANALYSIS ....................................................................................... 268

7.7.1 Finding the State Equations and Output Logic Expressions of an FSM ........ 268
7.7.2 Finding the State Transition Table of an FSM ................................................. 269
7.7.3 Finding the State Diagram of an FSM ............................................................. 270
7.7.4 Determining the Maximum Clock Frequency of an FSM ................................ 271
8: VERILOG (PART 2) .................................................................................................. 287
8.1 PROCEDURAL ASSIGNMENT ........................................................................................... 287
8.1.1 Procedural Blocks ............................................................................................ 287
8.1.2 Procedural Statements .................................................................................... 290
8.1.3 Statement Groups ............................................................................................ 295
8.1.4 Local Variables ................................................................................................ 295
8.2 CONDITIONAL PROGRAMMING CONSTRUCTS .................................................................... 296
8.2.1 if-else Statements ............................................................................................ 296
8.2.2 case Statements .............................................................................................. 297
8.2.3 casez and casex Statements .......................................................................... 299
8.2.4 forever Loops ................................................................................................... 299
8.2.5 while Loops ...................................................................................................... 299
8.2.6 repeat Loops .................................................................................................... 300
8.2.7 for Loops .......................................................................................................... 300
8.2.8 disable .............................................................................................................. 301
8.3 SYSTEM TASKS ........................................................................................................... 302
8.3.1 Text Output ...................................................................................................... 302
8.3.2 File Input/Output .............................................................................................. 303
8.3.3 Simulation Control and Monitoring .................................................................. 305
8.4 TEST BENCHES .......................................................................................................... 306
8.4.1 Common Stimulus Generation Techniques .................................................... 307
8.4.2 Printing Results to the Simulator Transcript .................................................... 308
8.4.3 Automatic Result Checking ............................................................................. 309
8.4.4 Using Loops to Generate Stimulus ................................................................. 311
8.4.5 Using External Files in Test Benches .............................................................. 312
9: BEHAVIORAL MODELING OF SEQUENTIAL LOGIC ............................................ 319
9.1 MODELING SEQUENTIAL STORAGE DEVICES IN VERILOG ................................................... 319
9.1.1 D-Latch ............................................................................................................ 319
9.1.2 D-Flip-Flop ....................................................................................................... 320
9.1.3 D-Flip-Flop with Asynchronous Reset ............................................................. 320
9.1.4 D-Flip-Flop with Asynchronous Reset and Preset .......................................... 321
9.1.5 D-Flip-Flop with Synchronous Enable ............................................................. 322
9.2 MODELING FINITE STATE MACHINES IN VERILOG .............................................................. 323
9.2.1 Modeling the States ......................................................................................... 325
9.2.2 The State Memory Block ................................................................................. 325
9.2.3 The Next-State Logic Block ............................................................................. 325
9.2.4 The Output Logic Block ................................................................................... 326
9.2.5 Changing the State Encoding Approach ......................................................... 328
 Contents • xv

9.3 FSM DESIGN EXAMPLES IN VERILOG ............................................................................ 329

9.3.1 Serial Bit Sequence Detector in Verilog .......................................................... 329
9.3.2 Vending Machine Controller in Verilog ............................................................ 331
9.3.3 2-Bit, Binary Up/Down Counter in Verilog ....................................................... 333
9.4 MODELING COUNTERS IN VERILOG ................................................................................ 335
9.4.1 Counters in Verilog Using a Single Procedural Block ..................................... 335
9.4.2 Counters with Range Checking ....................................................................... 336
9.4.3 Counters with Enables in Verilog .................................................................... 336
9.4.4 Counters with Loads ........................................................................................ 337
9.5 RTL MODELING ......................................................................................................... 338
9.5.1 Modeling Registers in Verilog .......................................................................... 338
9.5.2 Registers as Agents on a Data Bus ................................................................ 339
9.5.3 Shift Registers in Verilog ................................................................................. 341
10: MEMORY ................................................................................................................ 347
10.1 MEMORY ARCHITECTURE AND TERMINOLOGY ................................................................... 347
10.1.1 Memory Map Model ......................................................................................... 347
10.1.2 Volatile vs. Nonvolatile Memory ...................................................................... 348
10.1.3 Read Only vs. Read/Write Memory ................................................................ 348
10.1.4 Random Access vs. Sequential Access ......................................................... 348
10.2 NONVOLATILE MEMORY TECHNOLOGY ............................................................................ 349
10.2.1 ROM Architecture ............................................................................................ 349
10.2.2 Mask Read Only Memory ................................................................................ 352
10.2.3 Programmable Read Only Memory ................................................................ 353
10.2.4 Erasable Programmable Read Only Memory ................................................. 354
10.2.5 Electrically Erasable Programmable Read Only Memory .............................. 356
10.2.6 FLASH Memory ............................................................................................... 357
10.3 VOLATILE MEMORY TECHNOLOGY .................................................................................. 358
10.3.1 Static Random-Access Memory ...................................................................... 358
10.3.2 Dynamic Random-Access Memory ................................................................. 361
10.4 MODELING MEMORY WITH VERILOG ............................................................................... 368
10.4.1 Read Only Memory in Verilog ......................................................................... 368
10.4.2 Read/Write Memory in Verilog ........................................................................ 369
11: PROGRAMMABLE LOGIC ..................................................................................... 375
11.1 PROGRAMMABLE ARRAYS ............................................................................................. 375
11.1.1 Programmable Logic Array (PLA) ................................................................... 375
11.1.2 Programmable Array Logic (PAL) .................................................................... 376
11.1.3 Generic Array Logic (GAL) .............................................................................. 377
11.1.4 Hard Array Logic (HAL) ................................................................................... 378
11.1.5 Complex Programmable Logic Devices (CPLD) ............................................. 378
11.2 FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) ............................................................ 379
11.2.1 Configurable Logic Block (or Logic Element) .................................................. 380
11.2.2 Look-Up Tables (LUTs) .................................................................................... 381
11.2.3 Programmable Interconnect Points (PIPs) ...................................................... 384
xvi • Contents

11.2.4 Input/Output Block (IOBs) ................................................................................ 385

11.2.5 Configuration Memory ..................................................................................... 386
12: ARITHMETIC CIRCUITS ........................................................................................ 389
12.1 ADDITION ................................................................................................................... 389
12.1.1 Half Adders ...................................................................................................... 389
12.1.2 Full Adders ...................................................................................................... 390
12.1.3 Ripple Carry Adder .......................................................................................... 392
12.1.4 Carry Look Ahead Adder ................................................................................. 394
12.1.5 Adders in Verilog ............................................................................................. 397
12.2 SUBTRACTION ............................................................................................................. 402
12.3 MULTIPLICATION .......................................................................................................... 405
12.3.1 Unsigned Multiplication ................................................................................... 405
12.3.2 A Simple Circuit to Multiply by Powers of Two ................................................ 408
12.3.3 Signed Multiplication ....................................................................................... 408
12.4 DIVISION .................................................................................................................... 411
12.4.1 Unsigned Division ............................................................................................ 411
12.4.2 A Simple Circuit to Divide by Powers of Two .................................................. 414
12.4.3 Signed Division ................................................................................................ 415
13: COMPUTER SYSTEM DESIGN ............................................................................. 419
13.1 COMPUTER HARDWARE ............................................................................................... 419
13.1.1 Program Memory ............................................................................................. 420
13.1.2 Data Memory ................................................................................................... 420
13.1.3 Input/Output Ports ........................................................................................... 420
13.1.4 Central Processing Unit ................................................................................... 421
13.1.5 A Memory-Mapped System ............................................................................. 422
13.2 COMPUTER SOFTWARE ................................................................................................ 424
13.2.1 Opcodes and Operands .................................................................................. 425
13.2.2 Addressing Modes ........................................................................................... 425
13.2.3 Classes of Instructions .................................................................................... 426
13.3 COMPUTER IMPLEMENTATION: AN 8-BIT COMPUTER EXAMPLE ........................................... 433
13.3.1 Top-Level Block Diagram ................................................................................ 433
13.3.2 Instruction Set Design ..................................................................................... 434
13.3.3 Memory System Implementation ..................................................................... 435
13.3.4 CPU Implementation ....................................................................................... 439
13.4 ARCHITECTURE CONSIDERATIONS .................................................................................. 460
13.4.1 Von Neumann Architecture ............................................................................. 460
13.4.2 Harvard Architecture ....................................................................................... 460
14: FLOATING-POINT SYSTEMS ................................................................................ 465
14.1 OVERVIEW OF FLOATING-POINT NUMBERS ...................................................................... 465
14.1.1 Limitations of Fixed-Point Numbers ................................................................ 465
14.1.2 The Anatomy of a Floating-Point Number ...................................................... 466
14.1.3 The IEEE 754 Standard .................................................................................. 467
Exploring the Variety of Random
Documents with Different Content
 “Which are of very recent introduction and very insecure tenure,”
added I.
“They formed the corner-stone of the great charter on which our
English state is built—a charter that has become our glory and the
world’s envy.”
“To be broken into and rifled within a century; to be set under the
foot of a Henry VIII. and pinned to the petticoat of an Elizabeth; to
be mocked at in the death of a Mary, Queen of Scots, and a Charles;
to be thrown out of window by a Cromwell. Our charters and our
liberties! Oh! we are a thrifty race. We can pocket them all when it
suits our convenience, and flaunt them to the world on exhibition-
days. Our charter did not save young Raymond Herbert his neck for
sticking to his faith during the Reformation, though I believe that
same charter provided above all things that the church of God
should be free; and a Chief-Justice Herbert sat on the bench and
pronounced sentence on the boy, not daring to wag a finger in
defence of his own flesh and blood. Of course the Catholic Church
was not the church of God, for so the queen’s majesty decreed; and
to Chief-Justice Herbert we owe these lands, such of them as were
saved. Great heaven! we talk of nobility—English nobility; the
proudest race under the sun. The proudest race under the sun, who
would scorn to kiss the Pope’s slipper, grovelled in the earth, one
and all of them, under the heel of an Elizabeth, and the other day
trembled at the frown of a George the Fourth!”
I need not dwell on the fact that in those days I had a particular
fondness for the sound of my own voice. I gloried in what seemed to
me startling paradoxes, and flashes of wisdom that loosened bolts
and rivets of prejudice, shattered massive edifices of falsehood,
undermined in a twinkling social and moral weaknesses, which, of
course, had waited in snug security all these long years for my
coming to expose them to the scorn of a wondering world. What a
hero I was, what a trenchant manner I had of putting things, what a
keen intellect lay concealed under that calm exterior, and what a
deep debt the world would have owed me had it only listened in
time to my Cassandra warnings, it will be quite unnecessary for me
to point out.
“I suppose I ought to be very much ashamed of myself,” said
Kenneth good-humoredly; “but I still confess that I find my own
country the most interesting of any that I have seen. It may be that
the very variety, the strange contradictions in our national life and
character, noticed by our radical here, are in themselves no small
cause for that interest. If we have had a Henry VIII., we have had
an Alfred and an Edward; if we have had an Elizabeth, we have also
had a Maud; if our nobles cowered before a woman, they faced a
man at Runnymede, and at their head were English churchmen,
albeit not English churchmen of the stamp of to-day. If we broke
through our charter, let us at least take the merit of having restored
something of it, although it is somewhat mortifying to find that
centuries of wandering and of history and discovery only land us at
our old starting-point.”
“I give in. Bah! we are spoiling the night with history, while all
nature is smiling at us in her beautiful calm.”
“Ah! you have driven away the nightingale; it sings no more,” said
Fairy.
“Surely some one can console us for its absence,” said Kenneth,
glancing at Nellie.
“I do not understand Italian,” she laughed back.
“Your denial is a confession of guilt. I heard Roger call you Fairy.
There be good fairies and bad. You would not be placed among the
bad?”
“Why not?”
“Because all the bad fairies are old.”
“And ride on broomsticks,” added I.
Unlike her brother, who had not a note of music in him, Fairy had
a beautiful voice, which had had the additional advantage of a very
careful cultivation. She sang us a simple old ballad that touched our
hearts; and when that was done, we insisted on another. Then the
very trees seemed to listen, the flowers to open as to a new
sunlight, and shed their sweetness in sympathy, as she sang one of
those ballads of sighs and tears, hope and despair and sorrowful
lamentation, caught from the heart of a nation whose feelings have
been stirred to the depths to give forth all that was in them in the
beautiful music that their poet has wedded to words. The ballad was
“The Last Rose of Summer,” and as the notes died away the foliage
seemed to move and murmur with applause, while after a pause the
nightingale trilled out again its wonderful song in rivalry. There was
silence for a short time, which was broken by Kenneth saying:
“I must break up Fairy-land, and go back to the Black Bull.”
But of this we would not hear. It was agreed that Kenneth should
take up his quarters with us. The conversation outlasted our usual
hours at Leighstone. Kenneth sustained the burden; and with a
wonderful grace and charm he did so. He had read as well as
travelled, and more deeply and extensively than is common with
men of his years; for his conversation was full of that easy and
delightful illustration that only a student whose sharp angles have
been worn off by contact with the world outside his study can
command and gracefully use, leaving the gem of knowledge that a
man possesses, be it small or great, perfect in its setting. Much of
what he related was relieved by some shrewd and happy remark of
his own that showed him a close observer, while a genial good-
nature and tendency to take the best possible view of things diffused
itself through all. It was late when my father said:
“Mr. Goodal, you have tempted me into inviting an attack of my
old enemy by sitting here so long. There is no necessity for your
going to-morrow, is there, since you are simply on a walking tour?
Roger is a great rambler, and there are many pretty spots about
Leighstone, many an old ruin that will repay a visit. Indeed, ruins are
the most interesting objects of these days. My walking days, I fear,
are over. A visitor is a Godsend to us down here, and, though you
ramblers soon tire of one spot, there is more in Leighstone than can
be well seen in a day.”
Thus pressed, he consented, and our little party broke up.
“Are you an owl!” I asked Kenneth, as my father and sister retired.
“Somewhat,” he replied, smiling.
“Then come to my room, and you shall give your to-whoo to my
to-whit. I was born an owl, having been introduced into this world, I
am informed, in the small hours; and the habits of the species cling
to me. Take that easy-chair and try this cigar. These slippers will
ease your feet. Though not a drinking man, properly so called, I
confess to a liking for the juice of the grape. The fondness for it is
still strong in the sluggish blood of the Norse, and I cannot help my
blood. Therefore, at an hour like this, a night-cap will not hurt us. Of
what color shall it be? Of the deep claret tint of Bordeaux, the dark-
red hue of Burgundy, or the golden amber of the generous
Spaniard? Though, as I tell you, not a drinking man, I think a good
cigar and a little wine vastly improves the moonlight, provided the
quantity be not such as to obscure the vision of eye or brain. That is
not exactly a theory of my own. It was constantly and deeply
impressed upon me by a very reverend friend of mine, with whom I
read for a year. Indeed I fear his faith in port was deeper than his
faith in the Pentateuch. The drunkard is to me the lowest of animals,
ever has been, and ever will be. Were the world ruled—as it is
scarcely likely to be just yet—by my suggestions, the fate of the
Duke of Clarence should be the doom of every drunkard, with only
this difference; that each one be drowned in his own favorite liquor,
soaked there till he dissolved, and the contents ladled out and
poured down the throat of whoever, by any accident, mistook the
gutter for his bed. You will pardon my air; in my own room I am
supreme lord and master. Kenneth, my boy, I like you. I feel as
though I had known you all my life. That must have been the reason
for my unruly, ungracious, and unmannerly explosion down-stairs at
dinner. I have an uncontrollable habit of breaking out in that style
sometimes, and the effect on my father, whom I need not tell you I
love and revere above all men living, is what you see.”
He smoked in silence a few seconds, and then, turning on me,
suddenly asked:
“Where did you learn your theology?”
The question was the last in the world that would have presented
itself to me, and was a little startling, but put in too earnest a
manner for a sneer, and too kindly to give offence. I answered
blandly that I was guiltless of laying claim to any special theology.
“Well, your opinions, then—the faith, the reasons, on which you
ground your life and views of life. Your conversation at times drifts
into a certain tone that makes me ask. Where or what have you
studied?”
“Nowhere; nothing; everywhere; everything; everybody; I read
whatever I come across. And as for theology—for my theology, such
as it is—I suppose I am chiefly indebted to that remarkably clever
organ of opinion known as the Journal of the Age.”
A few whiffs in silence, and then he said:
“I thought so.”
“What did you think?”
“That you were a reader of the Journal of the Age. Most
youngsters who read anything above a sporting journal or a
sensational novel are. I have been a student of it myself—a very
close student. I knew the editor well. We were at one time bosom
friends. He took me in training, and I recognized the symptoms in
you at once.”
“How so?”
“The Journal of the Age—and it has numerous admirers and
imitators—is, in these days, the ablest organ of a great and almost
universal worship of an awful trinity that has existed since man was
first created; and the name of that awful trinity is—the devil, the
world, and the flesh.”
I stared at him in silent astonishment. All the gayety of his
manner, all its softness, had gone, and he seemed in deadly earnest,
as he went on:
“This worship is not paraded in its grossest form. Not at all. It is
graced by all that wit can give and undisciplined intellect devise. It
has a brilliant sneer for Faith, a scornful smile for Hope, and a chill
politeness for Charity. I revelled in it for a time. Heaven forgive me! I
was happy enough to escape.”
“With what result?”
“Briefly with this: with the conviction that man did not make this
world; that he did not make himself, or send himself into it; that
consequently he was not and could never be absolutely his own
master; that he was sent in and called out by Another, by a Greater
than he, by a Creator, by a God. I became and am a Catholic, to find
that what for a time I had blindly worshipped were the three
enemies against whom I was warned to fight all the days of my life.”
“And the Journal of the Age?”
“The editor cut me as soon as he found I believed in God in
preference to himself. He is the fiercest opponent of Papal Infallibility
with whom I ever had the honor of acquaintance.”
“I cannot say that your words and the manner in which you speak
them do not impress me. Still, it never occurred to me that so
insignificant a being as Roger Herbert was worthy the combined
attack of the three formidable adversaries you have named. What
have the devil, the world, and the flesh to do with me?”
“Yes, there is the difficulty, not only with Roger Herbert, but with
everybody else. It does seem strange that influences so powerful
and mysterious should be for ever ranged against such wretched
little beings as we are, whom a toothache tortures and a fever kills.
Yet surely man’s life on earth is not all fever and its prevention,
toothache and its cure, or a course of eating, doctoring, and
tailoring. If we believe at all in a life that can never end, in a soul,
surely that is something worth thought and care. An eternal life that
must range itself on one side or the other seems worthy of a
struggle between the powers of good and evil, if good and evil there
be. Nay, man is bound of his own right, of his own free will, of his
very existence, to choose between one and the other, to be good or
be bad, and not stumble on listlessly as a thing of chance, tossed at
will from one to the other. We do not sufficiently realize the greatest
of our obligations. We should feel disgraced if we did not pay our
tailor or our wine-merchant; but such a thought never presents itself
to us when the question concerns God or the devil, or that part of us
that does not wear clothes and does not drink wine.”
He had risen while he was speaking, and spoke with an energy
and earnestness I had never yet witnessed in any man. Whether
right or wrong, his view of things towered so high above my own
blurred and crooked vision that I felt myself crouch and grow small
before him. The watch-tower of his faith planted him high up among
the stars of heaven, while I groped and struggled far away down in
the darkness. Oh! if I could only climb up there and stand with him,
and see the world and all things in it from that divine and serene
height, instead of impiously endeavoring to build up my own and
others’ little Babel that was to reach the skies and enable us to
behold God. But conversions are not wrought by a few sentences
nor by the mere emotions of the heart; not by Truth itself, which is
for ever speaking, for ever standing before and confronting us, its
mark upon its forehead, yet we pass it blindly by; for has it not been
said that “having eyes they see not, and having ears they hear not”?
“Kenneth,” I said, stretching out my hand, which he clasped in
both of his, “the subject which has been called up I feel to be far too
solemn to be dismissed with the sneer and scoff that have grown
into my nature. Indeed, I always so regarded it secretly; but perhaps
the foolish manner in which I have hitherto treated it was owing
somewhat to the foolish people with whom I have had to deal from
my boyhood. They give their reasons about this, that, and the other
as parrots repeat their lesson, with interjectory shrieks and
occasional ruffling of the poll, all after the same pattern. You seem
to me to be in earnest; but, if you please, we will say no more about
it—at least now.”
“As you please,” he replied. “Here I am at the end of my cigar. So
good-night, my dear boy. Well, you have had my to-whit to your to-
whoo.”
And so a strange day ended. I sat thinking some time over our
conversation. Kenneth’s observations opened quite a new train of
thought. It had never occurred to me before that life was a great
battle-field, and that all men were, as it were, ranged under two
standards, under the folds of which they were compelled to fight.
Everything had come to me in its place. A man might have his
private opinions on men and things, as he collects a private museum
for his own amusement; but in the main one lived and died, acted
and thought, passed through and out of life, in much the same
manner as his neighbor, not inquiring and not being inquired into too
closely. Life was made for us, and we lived it much in the same way
as we learned our alphabet, we never knew well how, or took our
medicine, in the regulation doses. Sometimes we were a little
rebellious, and suffered accordingly; that was all. Excess on any side
was a bore to everybody else. It was very easy, and on the whole
not unpleasant. We nursed our special crotchets, we read our
newspapers, we watched our children at their gambols, we chatted
carelessly away out on the bosom of the broad stream along which
we were being borne so surely and swiftly into the universal goal.
Why should we scan the sky and search beneath the silent waters,
trembling at storms to come and treacherous whirlpools, hidden
sand-banks, and cruel rocks on which many a brave bark had gone
down? Chart and compass were for others; a pleasant sail only for
us. There was a Captain up aloft somewhere; it was his duty and not
ours to see that all was right and taut—ours to glide along in
slumbrous ease, between eternal banks of regions unexplored; to
feast our eyes on fair scenes, and lap our senses in musical repose.
That was the true life. Sunken rocks, passing storms, mutinies
among the crew, bursting of engines—what were such things to us?
Had we not paid our fares and made our provision for the voyage,
and was not the Captain bound to land us safely at our journey’s
end, if he valued his position and reputation?
The devil, the world, and the flesh! What nightmare summoned
these up, and set them glaring horribly into the eyes of a peaceful
British subject? What had the devil to do with me or I with the devil?
What were the world and the flesh? Take my father, now; what had
they to do with him? Or Fairy? Why, her life was as pure as that sky
that smiled down upon her with all its starry eyes. Let me see; there
were others, however, who afforded better subjects for investigation.
Whenever you want to find out anything disagreeable, call on your
friends and neighbors. There was the Abbot Jones, now; let us
weigh him in the triple scale. How fared the devil, the world, and the
flesh with the Abbot Jones? He was, as I said to Kenneth, a very
genial man; he had lived a good life, married into an excellent
family, paid his bills, had a choice library, a good table, was an
excellent judge of cattle, and a preacher whom everybody praised.
Abbot Jones was faultless! There was not a flaw to be found in him
from the tip of his highly-polished toe to the top of his highly-
polished head. He had a goodly income, but he used it cautiously;
for Clara and Alice were now grown up, and were scarcely girls to
waste their lives in a nunnery, like my cousins, the daughters of
Archdeacon Herbert, who adored all that was sweetly mortifying and
secluded, yet, by one of those odd contradictions in female and
human nature generally, never missed a fashion or a ball. Yes, Abbot
Jones was a good and exemplary man. To be sure, he did not walk
barefoot or sandal-shod, not alone among the highways, where men
could see and admire, but into the byways of life, down among the
alleys of the poor, where clustered disease, drunkenness, despair,
death; where life is but one long sorrow. But then for what purpose
did he pay a curate, unless to do just this kind of dirty, apostolic
work, while the abbot devoted himself to the cares of his family, the
publication of an occasional pamphlet, and that pleasant drawing-
room religion that finds its perfection in good dinners, sage maxims,
and cautious deportment? If the curate neglected his duty, that was
clearly the curate’s fault, and not the abbot’s. If the abbot were
clothed, not exactly in purple, but in the very best of broadcloth, and
fasted only by the doctor’s orders, prayed not too severely, fared
sumptuously every day of his life, he paid for every inch of cloth,
every ounce of meat, every drop of that port for which his table was
famous; for he still clung to the clerical taste for a wine that at one
time assumed a semi-ecclesiastical character, and certain crumbs
from his table went now and then to a stray Lazarus. Yes, he was a
faultless man, as the world went. He did not profess to be consumed
with the zeal for souls. His life did not aim at being an apostolic one.
He had simply adopted a profitable and not unpleasant profession. If
a S. Paul had come, straggling, footsore, and weary, into Leighstone,
and begun preaching to the people and attacking shepherds who
guarded not their fold, but quietly napped and sipped their port,
while the wolves of irreligion, of vice and misery in every form,
entered in and rent the flock from corner to corner, the abbot would
very probably have had S. Paul arrested for a seditious vagrant and
a disturber of the public peace.
Take my uncle, the archdeacon; what thought he of the world, the
flesh, and the devil? As for the last-named enemy of the human
race, he did not believe in him. A personal devil was to him simply a
bogy wherewith to frighten children. It was the outgrowth of
mediæval superstition, a Christianized version of a pagan fable. The
devil was a gay subject with Archdeacon Herbert, who was the
wittiest and courtliest of churchmen. His mission was up among the
gods of this world; his confessional ladies’ boudoirs, his penance an
epigram, his absolution the acceptance of an invitation to dinner. He
breathed in a perfumed atmosphere; his educated ear loved the
rustle of silks; he saw no heaven to equal a coach-and-four in Rotten
Row during the season. It was in every way fitting that such a man
should sooner or later be a bishop of the Church Established. He was
an ornament to his class—a man who could represent it in society as
well as in the pulpit, whose presence distilled dignity and perfume,
and whose views were what are called large and liberal—that is to
say, no “views” at all. What the three enemies had to do with my
uncle I could not see. I could only see that he would scarcely have
been chosen as one of The Twelve; but then who would be chosen
as one of The Twelve in these days?
I went to the window and looked out. The moon was going down
behind S. Wilfrid’s, and Leighstone was buried in gloomy shadow.
Down there below me in the darkness throbbed thousands of hearts
resting a little in peaceful slumber till the morning came to wake
them again to the toil and the struggle, the pleasure and the pain,
the good and the evil, of another day. The good and the evil. Was
there no good and evil waiting down there by the bedside of every
one, to face them in the morning, and not leave them until they
returned to that bedside at night? Was there a great angel
somewhere up above in that solemn, silent, ever-watchful heaven,
with an open scroll, writing down in awful letters the good and the
bad, the white and the black, in the life of each one of us? Were we
worth this care, weak little mortals, human machines, that we were?
What should our good or our evil count against the great Spirit,
whom we are told lives up above there in the passionless calm of a
fixed eternity? Did we shake our puny fists for ever in the face of
that broad, bent heaven that wrapped us in and overwhelmed us in
its folds, what effect would it have? If we held them up in prayer,
what profited it? Who of men could storm heaven or search hell?
And yet, as Kenneth said, a life that could not end was an awful
thing. That the existence we feel within us is never to cease; that
the power of discriminating between good and evil, define them,
laugh at them or quibble about them as we may, can never die out
of us; that we are irresistibly impelled to one or the other; that they
are always knocking at the door of our hearts, for we feel them
there; that they cannot be blind influences, knowing not when to
come or when to go, but the voices of keen intelligences acting over
the great universe, wherever man lives and moves and has his
being; that they are not creations of our own, for they are
independent of us; we may call evil good and good wicked, but in
the end the good will show itself, and the evil throw off its disguise
in spite of us—what does all this say but that there is an eternal
conflict going on, and that, will he or will he not, every man born
into the world must take a share in it?
That being so, search thine own heart, friend. Leave thy uncle,
leave thy neighbor, and come back to thyself. Let them answer for
their share; answer thou for thine. Which is thy standard? It cannot
be both. What part hast thou borne in the conflict? What giants
killed? What foes overcome? Hast thou slain that doughty giant
within thee—thine own self? Is there no evil in thee to be cast out?
No stain upon the scutcheon of thy pure soul? No vanity, no pride,
no love of self above all and before all, no worship of the world, no
bowing to Mammon or other strange gods, not to mention graver
blots than all of these? Let thy neighbor pass till all the dross is
purged out of thee. There is not a libertine in all the world but would
wish all the world better, provided he had not to become better with
it. Thy good wishes for others are shared by all men alike, by the
worst as by the best. Begin at home, friend, and root out and build
up there. Trim thy own garden, cast out the weeds, water and tend
it well. The very sight of it is heaven to the weary wayfarer who,
having wandered far away from his own garden, sinks down at thy
side, begrimed with the dust of the road and the smoke of sin. You
may tear him to pieces, you may lacerate his soul, you may cast
him, bound hand and foot, into the outer darkness, yet never touch
his heart. But he will stand afar off and admire when he sees thy
garden blowing fair, and all the winds of heaven at play there, all the
dews of heaven glistening there, all the sunshine of heaven beaming
there; then will he come and creep close up to thee, desiring to take
off the shoes from his feet, soiled with his many wanderings in foul
places. Then for the first time he feels that he has wandered from
the way, will see the stains upon him, and with trembling fingers
hasten to cast them off, and, standing barefoot and humble before
Him who made thee pure, falter out at length, “Lord, it is good for
us to be here.”
TO BE CONTINUED.
 CALDERON’S AUTOS SACRAMENTALES.
CONCLUDED.
II.

I. BALTASSAR’S FEAST.[55]

Of all Calderon’s autos, this is the one which has been the most
generally admired, both on account of its intense dramatic power
and popular character.
It has been translated several times into German (see note at end
of previous article on the autos), and into English by Mr. MacCarthy.
The latter says in his preface: “This auto must be classed with
those whose action relates directly to the Blessed Sacrament,
because it puts before us, in the profanation of the vases of the
Temple by Baltassar, a type of the desecration of the Holy
Sacrament, and symbolizes to us, in the punishment that follows this
sacrilege, the magnitude and sublimity of the Eucharistic Mystery.
Although this immediate relation between the action of the auto and
the sacrament becomes only manifestly clear in the last scene,
nevertheless all the preceding part, which is only preparing us for
the final catastrophe, stands in immediate connection with it, and,
through it, with the action of the auto. The wonderful simplicity of
this relation, and the lively dramatic treatment of the subject, allow
us to place this auto, justly, in the same category with those that,
comparatively speaking, are easy to be understood, and which, like
The Great Theatre of the World, have especial claims upon
popularity, even if many of its details contain very deep allusions, the
meaning of which, at first sight, is not very intelligible.”
The auto opens in the garden of Baltassar’s palace with a scene
between Daniel and Thought, who, dressed in a coat of many colors,
represents the Fool.
 After a long description of his abstract self he states that he has
this day been assigned to King Baltassar’s mind, and ironically
remarks that he, Thought, is not the only fool, and apologizes for his
rudeness in not listening to Daniel:

“It were difficult to try

To keep up a conversation,
We being in our separate station,
Wisdom thou, and Folly I.”

Daniel answers that there is no reason why they should not

converse, for the sweetest harmony is that which proceeds from two
different chords.
Thought hesitates no longer, and informs Daniel that he is thinking
of the wedding which Babylon celebrates this day with great
rejoicings. The groom is King Baltassar, son and heir of
Nabuchodonosor; the happy bride the fair Empress of the East,
Idolatry herself.
That the king is already wedded to Vanity is no hindrance, as his
law allows him a thousand wives.
Daniel breaks forth in lamentations for God’s people and the
unhappy kingdom; while clownish Thought asks if Daniel himself is
interested in the ladies, since he makes such an outcry over the
news, and insinuates that envy and his captivity are the causes of
his grief.
With a flourish of trumpets enter Baltassar and Vanity at one side,
and Idolatry, fantastically dressed, at the other, with attendants,
followers, etc.
The king courteously welcomes his new wife, who replies that it is
right that she should come to his kingdom, since here first after the
Flood idolatry arose.
 The king declares that his own idea, his sole ambition, has been to
unite Idolatry and Vanity, and then suddenly becomes absorbed in
thought while fondly regarding his wives; to their questions as to the
cause of his suspense he answers that, fired by their beauty, he
wishes to relate the wondrous story of his conquests.
Wonderful indeed is the story which follows, extending, in the
original, through three hundred and fifty uninterrupted lines.
In the introduction the king relates the strange fate of his father,
Nabuchodonosor, whose worthy successor he declares himself to be,
and describes his vaulting ambition, which will not be satisfied until
he is the sole ruler over all the region of Senaar, which beheld the
building of the Tower of Babel; this leads to an account of the
Deluge, so poetical and characteristic that we give its finest portion
here:[56]
“First began a dew as soft
As those tears the golden sunrise
Kisseth from Aurora’s lids;
Then a gentle rain, as dulcet
As those showers the green earth drinks
In the early days of summer;
From the clouds then water-lances,
Darting at the mountains, struck them;
In the clouds their sharp points shimmer’d,
On the mountains rang their but-ends;
Then the rivulets were loosened,
Roused to madness, ran their currents,
Rose to rushing rivers, then
Swelled to seas of seas. O Summit
Of all wisdom! thou alone
Knowest how thy hand can punish!
… Then a mighty sea-storm rushed
Through the rents and rocky ruptures,
By whose mouths the great earth yawns,
When its breath resounds and rumbles
From internal caves. The air
… Roared confined, the palpitation
Of its fierce internal pulses
Making the great hills to shake,
And the mighty rocks to tremble.
The strong bridle of the sand,
Which the furious onset curbeth
Of the white horse of the sea
With its foam-face silver fronted,
Loosened every curbing rein,
So that the great steed, exulting,
Rushed upon the prostrate shore,
With loud neighing to o’errun it.”
 The ark alone is saved, and Nimrod resolves to anticipate a second
Deluge, and erect a more ambitious refuge. The building of the
Tower of Babel and the Confusion of Tongues then follow, and the
king closes his long monologue with the determination to rebuild
Nimrod’s tower, urged to the task by the opportune conjunction of
Idolatry and Vanity.
These express their gratification at this lofty scheme, and offer to
perpetuate the fame of his great deeds.
The king, exulting, exclaims: “Who shall break this bond?”
Daniel, advancing, “The hand of God!” and returns the same
answer to the king’s angry question, “What can save thee from my
power or defend thee?”
Baltassar is profoundly moved, but spares Daniel because Vanity
loathes the captive and Idolatry disdains his religion.
In the fourth scene the prophet addresses the Most High, and
cries: “Who can endure these offences, these pretences of Vanity
and displays of Idolatry? Who will end so great an evil?”
“I will,” answers Death, who enters, wearing a sword and dagger,
and dressed symbolically in a cloak covered with figures of
skeletons.

Daniel. “Awful shape, to whom I bow

Through the shadowy glooms that screen thee,
Never until now I’ve seen thee:
Fearful phantom, who art thou?”

Death’s answer in the following monologue is most impressive and

beautiful. Our space, unfortunately, will let us quote but a part:
 “Daniel, thou Prophet of the God of Truth,
I am the end of all who life begin,
The drop of venom in the serpent’s tooth,
The cruel child of envy and of sin.
Abel first showed the world’s dark door uncouth,
But Cain threw wide the door, and let me in;
Since then I’ve darkened o’er life’s checker’d path,
The dread avenger of Jehovah’s wrath.
… The proudest palace that supremely stands,
’Gainst which the wildest winds in vain may beat;
The strongest wall, that like a rock withstands
The shock of shells, the furious fire-ball’s heat—
All are but easy triumphs of my hands,
All are but humble spoils beneath my feet;
If against me no palace-wall is proof,
Ah! what can save the lowly cottage-roof?
Beauty, nor power, nor genius, can survive,
Naught can resist my voice when I sweep by;
For whatsoever has been let to live,
It is my destined duty to see die.
With all the stern commands that thou mayst give,
I am, God’s Judgment, ready to comply;
Yea, and so quickly shall my service run
That ere the word is said the deed is done!”

Death then recounts some of his past achievements to prove his

readiness to inflict punishment on the king.
Daniel, however, expressly forbids him to kill Baltassar, and gives
him leave only to awaken him to a sense of coming woe and the fact
that he is mortal.
This Death does by appearing to the king and showing him a small
book lost by him some time before (i.e., the remembrance of his
mortality, which he had forgotten), in which is written his debt to
Death.
He leaves the terror-stricken monarch with an admonition to
remember his obligation.
Thought, hovering between Vanity and Idolatry, soon, however,
effaces the impression left by the terrible visitor.
The king and Thought, lulled by their combined flatteries, fall
asleep, while Death enters and delivers the following monologue,
which, as Mr. MacCarthy truly says, “belongs unquestionably to the
deepest and most beautiful poetry that has ever flown from the pen
of Calderon”:
 Death. “Man the rest of slumber tries,
Never the reflection making
That, O God! asleep and waking,
Every day he lives and dies;
That a living corse he lies,
After each day’s daily strife,
Stricken by an unseen knife,
In brief lapse of life, not breath,
A repose which is not death;
But what is death teaches life:
Sugared poison ’tis, which sinks
On the heart, which it o’ercometh,
Which it hindereth and benumbeth.
And can a man, then, live who poison drinks?
’Tis forgetting, when the links
That gave life by mutual fretting
To the Senses, snap, or letting
The imprisoned Five go free,
They can hear not, touch, or see;
And can a man forget this strange forgetting?
It is frenzy, that which moves
Heart and eyes to taste and see
Joys and shapes that ne’er can be:
And can a man be found who frenzy loves?
’Tis a lethargy that proves
My best friend; in trust for me,
Death’s dull, drowsy weight bears he,
And, by failing limb and eye,
Teaches man the way to die:
And can a man, then, seek this lethargy?
’Tis a shadow, which is made
Without light’s contrasted aid,
Moving in a spectral way,
Sad, phantasmal foe of day:
And can a man seek rest beneath such shade?